Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Po-Hsien Cheng"'
Publikováno v:
Scientific Reports, Vol 7, Iss 1, Pp 1-9 (2017)
Abstract Metallic channel transistors have been proposed as the candidate for sub-10 nm technology node. However, the conductivity modulation in metallic channels can only be observed at low temperatures usually below 100 K. In this study, room-tempe
Externí odkaz:
https://doaj.org/article/4b63f1a5b5514f2fb287c1796b917329
Autor:
Po-Hsien Cheng, 鄭柏賢
107
In the sub-10nm semiconductor technology nodes, the major issue is the power consumption. Due to the challenge of extreme process conditions for the nanofabrication, the variability and stability issues for continuous transistor scaling have
In the sub-10nm semiconductor technology nodes, the major issue is the power consumption. Due to the challenge of extreme process conditions for the nanofabrication, the variability and stability issues for continuous transistor scaling have
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/mb897f
Publikováno v:
ACS Applied Nano Materials. 2:4578-4583
Conformal atomic layer etching (cALE) of Si is realized on the basis of layer-by-layer self-limiting deposition and self-stop etching processes at low temperatures. In each cALE cycle, a conformal ...
Autor:
Yu-Tung Yin, Makoto Shiojiri, Jing-Jong Shyue, Po-Hsien Cheng, Hsin-Chih Lin, Wei-Hao Lee, Miin-Jang Chen
Publikováno v:
ACS Sustainable Chemistry & Engineering. 7:487-495
Heteroepitaxy with large thermal and lattice mismatch between the semiconductor and substrate is a critical issue for high-quality epitaxial growth. Typically, high growth temperatures (>1000 °C) a...
Autor:
Cheng‐Ming Lin, Chuang‐Han Hsu, Wei‐Yu Huang, Vincent Astié, Po‐Hsien Cheng, Yue‐Min Lin, Wei‐Shan Hu, Szu‐Hua Chen, Han‐Yu Lin, Ming‐Yang Li, Blanka Magyari‐Kope, Chi‐Ming Yang, Jean‐Manuel Decams, Tzu‐Lih Lee, Dong Gui, Han Wang, Wei‐Yen Woon, Pinyen Lin, Jeff Wu, Jang‐Jung Lee, Szuya Sandy Liao, Min Cao
Publikováno v:
Advanced Materials Technologies. 7:2200022
Publikováno v:
Applied Surface Science. 443:421-428
Sub-10 nm high-K gate dielectrics are of critical importance in two-dimensional transition metal dichalcogenides (TMDs) transistors. However, the chemical inertness of TMDs gives rise to a lot of pinholes in gate dielectrics, resulting in large gate
Publikováno v:
Journal of Applied Physics; 2017, Vol. 122 Issue 9, p1-5, 5p, 2 Diagrams, 6 Graphs
Publikováno v:
Scientific Reports, Vol 7, Iss 1, Pp 1-9 (2017)
Scientific Reports
Scientific Reports
Metallic channel transistors have been proposed as the candidate for sub-10 nm technology node. However, the conductivity modulation in metallic channels can only be observed at low temperatures usually below 100 K. In this study, room-temperature fi
Autor:
Makoto Shiojiri, Po-Hsien Cheng, Lain-Jong Li, Yu-Tung Yin, I-Na Tsai, Chen-Hsuan Lu, Samuel C. Pan, Jay Shieh, Miin-Jang Chen
Publikováno v:
Communications Physics, Vol 2, Iss 1, Pp 1-8 (2019)
Negative capacitance (NC) has been proposed to realize sub-Boltzmann steep-slope transistors in recent years. We provide experimental evidences and theoretical view for ferroelectric NC and inductance induced by polarization switching, based on an as
Publikováno v:
Scientific Reports
It is very difficult to realize sub-3 nm patterns using conventional lithography for next-generation high-performance nanosensing, photonic and computing devices. Here we propose a completely original and novel concept, termed self-shrinking dielectr