Zobrazeno 1 - 10
of 20
pro vyhledávání: '"Po Yen Chiu"'
Autor:
Po Yen Chiu, 邱博雁
102
Cloud parallel computing is several times faster than traditional stand-alone equipment. Cloud means network, and parallel computing is to increase the number of operations by tandem computers and thus to accelerate computing. Cloud computin
Cloud parallel computing is several times faster than traditional stand-alone equipment. Cloud means network, and parallel computing is to increase the number of operations by tandem computers and thus to accelerate computing. Cloud computin
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/4446mq
Publikováno v:
Pharmacognosy Magazine. 19:295-302
Background Cisplatin, the first-line drug for chemotherapy, often has limited treatment efficacy because of resistance and cancer recurrence mechanisms. Tetrandrine is a unique secondary metabolite of Stephania tetrandra. As a traditional Chinese med
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::058d36e93c40158e86e3786b451c2da2
https://doi.org/10.1177/09731296231158699
https://doi.org/10.1177/09731296231158699
Publikováno v:
Emirates Journal of Food & Agriculture (EJFA); 2023, Vol. 35 Issue 12, p1-8, 8p
Publikováno v:
The Journal of veterinary medical science. 84(8)
Corni fructus is consumed as food and herbal medicine in Chinese culture. Studies have revealed that corni fructus exhibits potent antioxidant activity; however, few studies have investigated the ability of corni fructus to lower uric acid concentrat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0eac023b7feb72c20f0e9e698010103c
https://pubmed.ncbi.nlm.nih.gov/35781421
https://pubmed.ncbi.nlm.nih.gov/35781421
Publikováno v:
IEEE Transactions on Electron Devices. 64:642-645
Due to the snapback holding voltage of high-voltage (HV) nMOS smaller than the maximum operating voltage, the traditional power-rail electrostatic discharge (ESD) clamp circuit implemented with such HV nMOS suffered latchup-like failure in a touch pa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a4be0c070731cc0164c49a0897d1708b
https://doi.org/10.1109/ted.2016.2642042
https://doi.org/10.1109/ted.2016.2642042
Autor:
Ming-Dou Ker, Po Yen Chiu
Publikováno v:
Microelectronics Reliability. 54:64-70
Between the metal–insulator–metal (MIM) capacitor and metal–oxide–metal (MOM) capacitor, the MIM capacitor has a better characteristic of stable capacitance. However, the MOM capacitors can be easily realized through the metal interconnection
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::db1d425166f5d82e2a8edbb9c71e8c62
https://doi.org/10.1016/j.microrel.2013.08.011
https://doi.org/10.1016/j.microrel.2013.08.011
Autor:
Ming-Dou Ker, Po-Yen Chiu
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 60:2549-2560
A new 2×VDD-tolerant input/output (I/O) buffer with process, voltage, and temperature (PVT) compensation is proposed and verified in a 90-nm CMOS process. Consisting of the dynamic source bias and gate controlled technique, the proposed mixed-voltag
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4a0b791049acd6dd38ff8112d03ba71e
https://doi.org/10.1109/tcsi.2013.2244351
https://doi.org/10.1109/tcsi.2013.2244351
Autor:
Ming-Dou Ker, Po-Yen Chiu
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 11:474-483
A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit designed with consideration of the gate leakage issue has been proposed and verified in a 65-nm low-voltage CMOS process. Consisting of the new low-leakage ESD-detection circuit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e6a17cbd6e78a9edad1ad9771343aa34
https://doi.org/10.1109/tdmr.2010.2066976
https://doi.org/10.1109/tdmr.2010.2066976
Autor:
Po-Yen Chiu, Ming-Dou Ker
Publikováno v:
SoCC
The novel 2×VDD NOT, NAND, and NOR logic gates have been designed and implemented in a nanoscale CMOS process with only 1×VDD devices. With the proposed dynamic source bias technique, the logic gates can be designed to have 2×VDD tolerant capabili
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::327e51c698f9baeab6631071eff1056c
https://doi.org/10.1109/socc.2013.6749656
https://doi.org/10.1109/socc.2013.6749656
Publikováno v:
2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.
The ESD robustness of gate-driven ESD clamp circuit in a 16-V CMOS process was investigated by the stresses of transmission line pulse (TLP), human-body-model ESD test, and machine-model (MM) ESD test. After TLP stresses of different voltage steps, t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c6f9b0b857a7c0d836a14805654ca4b2
https://doi.org/10.1109/ipfa.2012.6306283
https://doi.org/10.1109/ipfa.2012.6306283