Výsledky vyhledávání - "Plesco, Alexandru"

Akademický článek

FPGA-specific synthesis of loop-nests with pipelined computational cores

Autor: Alias, Christophe, Pasca, Bogdan, Plesco, Alexandru

Publikováno v: In Microprocessors and Microsystems November 2012 36(8):606-619

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High-Level Synthesis of Pipelined FSM from Loop Nests

Autor: Alias, Christophe, Rastello, Fabrice, Plesco, Alexandru

Publikováno v: [Research Report] 8900, INRIA. 2016, pp.18

Embedded systems raise many challenges in power, space and speed efficiency. The current trend is to build heterogeneous systems on a chip with specialized processors and hardware accelerators. Generating an hardware accelerator from a computational

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::5db3966c6010878a016a825491a6a831
https://hal.inria.fr/hal-01301334

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Akademický článek

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Procédé de synthèse de circuits, dispositif et programme d’ordinateur associés

Autor: Alias, Christophe, Plesco, Alexandru

Publikováno v: France, N° de brevet: FR1453308. 2014

La présente invention concerne un procédé de synthèse automatique de circuits comprenant une étape de compilation d’un programme logiciel en un réseau de processus réguliers interconnectés à l’aide de canaux, selon lequel chaque canal es

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::9a0e5b8c09114c8948b5d28e159191e4
https://inria.hal.science/hal-01096129

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Kernel Offloading with Optimized Remote Accesses

Autor: Alias, Christophe, Darte, Alain, Plesco, Alexandru

Publikováno v: [Research Report] RR-7697, INRIA. 2011, pp.29

The use of hardware accelerators, e.g., with GPGPUs or customized circuits using FPGAs, are particularly interesting for accelerating data- and compute-intensive applications. However, to get high performance when offloading computation kernels to su

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::c7dff4d70252d95c210f860feddeeef4
https://hal.inria.fr/inria-00611179

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FPGA-Specific Synthesis of Loop-Nests with Pipelined Computational Cores

Autor: Alias, Christophe, Pasca, Bogdan, Plesco, Alexandru

Publikováno v: [Research Report] RR-7674, INRIA. 2011, pp.33

Increases in the capacities and features of FPGAs has opened a new perspective on their use as application accelerators. However, in order for FPGAs to be accepted is mainstream solutions, the long design cycles must be shortened by using high-level

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::927348ded173b909a7e60baa97bc696b
https://hal.inria.fr/inria-00606977/file/RR-7674.pdf

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Program Analysis and Source-Level Communication Optimizations for High-Level Synthesis

Autor: Alias, Christophe, Darte, Alain, Plesco, Alexandru

Publikováno v: [Research Report] RR-7648, INRIA. 2011, pp.16

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::9aaea619a8b1adb74e0bf88e3c715de6
https://inria.hal.science/inria-00601822

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Program Transformations and Memory Architecture Optimizations for High-Level Synthesis of Hardware Accelerators

Autor: Plesco, Alexandru

Publikováno v: Other [cs.OH]. Ecole normale supérieure de lyon-ENS LYON, 2010. English

A wide category of sold products including telecommunication and multimedia propose more and more advanced features and functionalities. These functionalities come at a cost of increased design complexity. For performance and power budget issues, the

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=od_______212::3e0d241b3da2cfed09ef5369cb3a43ba
https://tel.archives-ouvertes.fr/tel-00544349

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Coupling Loop Transformations and High-Level Synthesis

Autor: Risset, Tanguy, Plesco, Alexandru

Publikováno v: Symposium en Architecture de machines (Sympa 2008)
Symposium en Architecture de machines (Sympa 2008), 2008, Fribourg, Switzerland

In this paper we present our study of adding an advanced preprocessing code transformation step to high-level synthesis (HLS) tools. Our approach is to use advanced state-of-the-art compiler frontend as an independent C-to-C preprocessing step before

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::3a83a1625a5d260b9e722353752187c8
https://hal.science/hal-00410724

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