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Publikováno v:
International Journal of Electronics and Electrical Engineering. :298-302
A proposed delay-locked loop (DLL) circuit that uses 4 cell delay line with extended inverters is proposed, designed and simulated in 180nm CMOS process technology. This design can be applied to microprocessors, memory, and communication IC applicati
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d48cd46d32b75084414990fc9a8bf308
https://doi.org/10.12720/ijeee.2.4.298-302
https://doi.org/10.12720/ijeee.2.4.298-302
