Zobrazeno 1 - 10
of 37
pro vyhledávání: '"Pinjala Damaruganath"'
Autor:
Ho Soon Wee, V.S. Rao, Pinjala Damaruganath, Ranjan Rajoo, Gaurav Sharma, V. N. Sekhar, Lim Ying Ying
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 2:13-22
In this paper, we present the evaluation results of low cure temperature (less than 200°C) dielectric materials (LCTDMs) in terms of processability and adhesion to silicon nitride and mold compound substrates. The results showed that the LCTDMs have
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::859b42c23d6a84c7c64c6fe321f374b3
https://doi.org/10.1109/tcpmt.2010.2104324
https://doi.org/10.1109/tcpmt.2010.2104324
Autor:
Pinjala Damaruganath, M Ravi, John H. Lau, Ebin Liao, Vempati Srinivasa Rao, Nagarajan Ranganathan, Hong Yu Li, Yen Yi Germaine Hoe, Jiangyan Sun, Xiaowu Zhang, Eva Wai, Tai Chong Chai, C. J. Vath, C. S. Selvanayagam, Y Tsutsumi, Yue Ying Ong, Shiguo Liu, Kripesh Vaidyanathan
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 1:660-672
The continuous push for smaller bump pitch interconnection in line with smaller Cu/low-k technology nodes demands the substrate technology to support finer interconnection. However, the conventional organic buildup substrate is facing a bottleneck in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::19099bdcb6f56725b6fe9bc40b06a81b
https://doi.org/10.1109/tcpmt.2010.2101911
https://doi.org/10.1109/tcpmt.2010.2101911
Autor:
Yap Guan Jie, Calivn Teo Wei Liang, Tan Chee Wei, Khoo Yee Mong, Germaine Hoe Yen Yi, Lim Teck Guan, Pinjala Damaruganath, P.V. Ramana, Joey Chai Yi Yoon
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 1:125-132
A simple and novel design, integrating discrete commercial micro-lens and vertical illuminated optoelectronic component in a substrate with high accuracy, is presented here. Without affecting the optical performances, this integrated optical carrier
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7fc0a688c94965059aa266ab987688f2
https://doi.org/10.1109/tcpmt.2010.2101810
https://doi.org/10.1109/tcpmt.2010.2101810
Autor:
Pinjala Damaruganath, D. Shashanka, Arun Chandrashekar, Shama Bhat, A. Raghav, B. R. Kirana, Prathap Babu Shetty, Suresh Kumar Rajendran
Publikováno v:
2013 International conference on Circuits, Controls and Communications (CCUBE).
Modern day innovations for applications in Life Sciences and Health Care are revolutionizing the public healthcare sector. Long gone are the days when advanced diagnostics were available only for the elite. Bringing these advancements in diagnostics
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3599306bc6cde06bb52fb56423d56d93
https://doi.org/10.1109/ccube.2013.6718568
https://doi.org/10.1109/ccube.2013.6718568
Autor:
Soon Wee Ho, Fernandez Moses Daniel, Wen-Sheng Lee, Pinjala Damaruganath, Myo Ei Pa Pa, Ser Choong Chong, Hyoung Joon Kim, Gao Shan
Publikováno v:
2011 IEEE 13th Electronics Packaging Technology Conference.
In this paper, a Via in Mold (ViM) interconnects were developed for embedded wafer level package (EMWLP) to enable 3D application. ViM interconnects are essentially plated blind vias drilled into the mold compound substrate. The two key processes req
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::03b3219e9dd4305e1d54a6ddbcafe6f2
https://doi.org/10.1109/eptc.2011.6184457
https://doi.org/10.1109/eptc.2011.6184457
Publikováno v:
2010 IEEE Electrical Design of Advanced Package & Systems Symposium.
Die stacking is widely adopted for high chip count systems to reduce the requirement of substrate area. The incorporation of Through-Silicon-Via (TSV) as vertical interconnects further reduces the interconnect path length from the top die to substrat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::160ae4c737667ac7b41bef4fce2f09c7
https://doi.org/10.1109/edaps.2010.5683014
https://doi.org/10.1109/edaps.2010.5683014
Autor:
Johnny He Han, Rakesh Kumar, Pinjala Damaruganath, Choi Won Kyoung, Li Shiah Lim, Ranganathan Nagarajan, Lam Quynh Trang, Aibin Yu, Yap Guan Jie, C. S. Premachandran
Publikováno v:
2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).
This paper discusses wafer level vacuum sealing technology with evaporated AuSn solder for a microelectromechanical systems (MEMS) resonator without getter material. The MEMS resonator is fabricated and characterized in a vacuum chamber. Relationship
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c6d2ca46cb434edf884aa5607959308c
https://doi.org/10.1109/ectc.2010.5490754
https://doi.org/10.1109/ectc.2010.5490754
Autor:
Rakesh Kumar, Ebin Liao, Pinjala Damaruganath, M. Chew, Soon Wee Ho, Nandar Su, C. S. Premachandran, V.S. Rao
Publikováno v:
2009 11th Electronics Packaging Technology Conference.
A dry film photoresist was selected as the sacrificial material for a metal lift off process. However, a weak and inconsistent adhesion of the evaporated under bump metallurgy (UBM) and solder on the passivation surface was observed during the dry fi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d8b6694e748f535b45c4374f0844602f
https://doi.org/10.1109/eptc.2009.5416418
https://doi.org/10.1109/eptc.2009.5416418
Autor:
Xiaowu Zhang, Liao Ebin, Vempati Srinivasa Rao, Chai Tai Chong, Ranganathan Nagarajan, Li Hong Yu, Lee Wen Sheng Vincent, Pinjala Damaruganath, Ho Soon Wee
Publikováno v:
2009 11th Electronics Packaging Technology Conference.
In this paper, Through silicon via (TSV) based interposer fabrication processes for 3D stack packaging has been presented. An interposer test chip of 25 × 25 mm size, has been designed with full array TSVs of 50 um size vias at 300 um pitch. TSVs of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ce1a2d67f5199685601ed69511ab29ea
https://doi.org/10.1109/eptc.2009.5416509
https://doi.org/10.1109/eptc.2009.5416509
Autor:
Vempati Srinivasa Rao, Xiaowu Zhang, Eipa Myo, Leong Ching Wai, Pinjala Damaruganath, Tai Chong Chai, Daquan Yu, Yue Ying Ong, Meei Leng Thew, Nandar Su, Ming Chinq Jong
Publikováno v:
2009 11th Electronics Packaging Technology Conference.
This paper presents the assembly optimization and charcterierization of Through-Silicon Vias (TSV) interposer technology for two 8 × 10mm2 micro-bumped chips. The two micro-bumped chips represent different functional dies in a System-in-package (SiP
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::26f1393df1d90610cd6b768b5a34b36e
https://doi.org/10.1109/eptc.2009.5416505
https://doi.org/10.1109/eptc.2009.5416505