Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Phillip Czeslaw Jozwiak"'
Autor:
Cong-Son Trinh, Phillip Czeslaw Jozwiak, Cornelius Christian Russ, Markus Paul Josef Mergens, John Armer, Russell Mohn, B. Keppens, K. Verhaege
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 5:532-542
A novel diode-triggered silicon-controlled rectifier (DTSCR) (Mergens et al., 2003) electrostatic discharge (ESD) protection element is introduced for low-voltage application (signal and supply voltages /spl les/ 1.8 V) with extremely narrow ESD desi
Autor:
S. Trinh, B. Van Camp, G. Taylor, B. Keppens, K. Verhaege, Phillip Czeslaw Jozwiak, Markus Paul Josef Mergens, John Armer, Russell Mohn, Cornelius Christian Russ, F. De Ranter
Publikováno v:
Microelectronics Reliability. 43:1537-1543
Autor:
Russ Mohn, Koen Verhaege, John Armer, Markus Paul Josef Mergens, Christian C. Russ, Phillip Czeslaw Jozwiak
Publikováno v:
Microelectronics Reliability. 43:993-1000
This paper presents a novel Silicon Controlled Rectifier (SCR) for power line and local I/O ESD protection. The High holding current SCRs (HHI-SCR) exhibits a dual ESD clamp characteristic: low-current high-voltage clamping and high-current low-volta
Autor:
Phillip Czeslaw Jozwiak, Markus Paul Josef Mergens, John Armer, K. Verhaege, Christian C. Russ
Publikováno v:
Microelectronics Reliability. 42:3-13
This paper presents three novel design techniques, which combined fulfill all major requirements posed on large driver and electrostatic discharge (ESD) protection transistors: minimum area consumption, good ESD robustness and optimized normal operat
Autor:
C. Russ, F. De Ranter, K. Verhaege, Geert Wybo, B. Keppens, Markus Paul Josef Mergens, B. Van Camp, John Armer, Phillip Czeslaw Jozwiak
Publikováno v:
ISCAS (2)
This paper presents a protection strategy for ultra-sensitive I/O containing thin gate oxides, while combining two complementary ESD design approaches: (1) low-voltage diode-chain triggered SCR clamps that allow for efficient voltage clamping; (2) ac
Autor:
K. Verhaege, B. Keppens, F. De Ranter, Markus Paul Josef Mergens, John Armer, R. Kumar, Phillip Czeslaw Jozwiak
Publikováno v:
CICC
This paper presents a novel active-source-pump (ASP) circuit technique to significantly lower the ESD sensitivity of ultrathin gate inputs in advanced sub-90nm CMOS technologies. As demonstrated by detailed experimental analysis, an ESD design window
Autor:
Phillip Czeslaw Jozwiak, K. Verhaege, B. Keppens, Cong Son Trinh, Cornelius Christian Russ, Markus Paul Josef Mergens, John Armer, Russell Mohn
Publikováno v:
IEEE International Electron Devices Meeting 2003.
A novel diode-triggered SCR (DTSCR) ESD protection element is introduced for low-voltage application (signal, supply voltage /spl les/1.8 V) and extremely narrow ESD design margins. Trigger voltage engineering in conjunction with fast and efficient S