Výsledky vyhledávání - "Philippe Lorenzini"

Hot-carrier evaluation of a zero-cost transistor developed via process optimization in an embedded non-volatile memory CMOS technology

Autor: Arnaud Regnier, Abderrezak Marzaki, Philippe Lorenzini, Franck Julien, Hassen Aziza, P. Devoge, Sebastien Haendler, Alexandre Malherbe, M. Mantelli, Julien Delalleau, Stephan Niel, T. Cabout

Publikováno v: Microelectronics Reliability
Microelectronics Reliability, 2021, 126, pp.114265. ⟨10.1016/j.microrel.2021.114265⟩
Microelectronics Reliability, Elsevier, 2021, 126, pp.114265. ⟨10.1016/j.microrel.2021.114265⟩

A new transistor architecture is developed by reusing already existing fabrication process bricks in an embedded non-volatile memory (eNVM) sub-40 nm CMOS technology, resulting in a middle-voltage zero-cost transistor, ideal for low-cost products. TC

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1ceb38e2dc7a527bff3df32e12cda2df
https://hal.science/hal-03500203

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Circuit-level evaluation of a new zero-cost transistor in a embedded non-volatile memory CMOS technology

Autor: Arnaud Regnier, Stephan Niel, Alexandre Malherbe, Abderrezak Marzaki, Sebastien Haendler, Hassen Aziza, Franck Julien, Thomas Sardin, M. Mantelli, Philippe Lorenzini, Paul Devoge

Publikováno v: 2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)
2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Jun 2021, Montpellier, France. pp.1-5, ⟨10.1109/DTIS53253.2021.9505137⟩
DTIS

International audience; This work presents a new transistor architecture developed by reusing already existing fabrication process steps in an embedded non-volatile memory (eNVM) CMOS technology. The proposed transistor is derived from an existing hi

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::906c65c22204cffd14cbbb4c054149ab
https://hal.archives-ouvertes.fr/hal-03502361/file/dtis21-22.pdf

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Study and Reduction of Variability in 28 nm Fully Depleted Silicon on Insulator Technology

Autor: Philippe Lorenzini, Gilles Jacquemod, Frederic Hameau, Emeric de Foucauld, Zhaopeng Wei, Yves Leduc

Publikováno v: Journal of Low Power Electronics. 12:64-73

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::aa46016cfa41fe7765b04e0301ce274a
https://doi.org/10.1166/jolpe.2016.1421

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Gate oxide degradation assessment by electrical stress and capacitance measurements

Autor: Olivier Gourhant, Pascal Masson, Franck Julien, Jerome Goy, Giada Ghezzi, Jean-Luc Ogier, Thibault Kempf, Dann Morillon, Clement Pribat, Alexandre Villaret, N. Cherault, Stephan Niel, Philippe Lorenzini

Publikováno v: 2018 International Integrated Reliability Workshop (IIRW).

In this paper, the reliability of thick SiO 2 gate oxides is assessed using quasi-static and multi-frequency capacitance measurements after constant current stress. A comprehensive study of oxide wear-out is presented, highlighting trapping mechanism

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::28a688c95ccd71cf239092391ae754d5
https://doi.org/10.1109/iirw.2018.8727082

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2.45 GHz 0.8 mW voltage-controlled ring oscillator (VCRO) in 28 nm fully depleted silicon-on-insulator (FDSOI) technology

Autor: Yves Leduc, Gilles Jacquemod, Philippe Lorenzini, Emeric de Foucauld, Alexandre Fonseca

Publikováno v: Frontiers of Materials Science. 9:156-162

MOS bulk transistor is reaching its limits: sub-threshold slope (SS), drain induced barrier lowering (DIBL), threshold voltage (VT) and VDD scaling slowing down, more power dissipation, less speed gain, less accuracy, variability and reliability issu

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::244ddc5ce672f0101640591627db9131
https://doi.org/10.1007/s11706-015-0288-6

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Study and reduction of variability in 28 nm FDSOI technology

Autor: Jad Modad, Frederic Hameau, Zhaopeng Wei, Yves Leduc, Emeric de Foucauld, Philippe Lorenzini, Gilles Jacquemod

Publikováno v: 2015 International Workshop on CMOS Variability (VARI).

This In this paper, we present a new inverter topology in order to decrease the process variability influence on performances of a ring oscillator. Using FDSOI technology, we used the back-gate electrode of the transistor to symmetrize the output of

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::9dbc566a3356fe01b471f2907c188b67
https://doi.org/10.1109/vari.2015.7456557

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VCO design in SOI technologies

Autor: Yves Leduc, Alexandre Fonseca, Emeric de Foucauld, Gilles Jacquemod, Philippe Lorenzini

Publikováno v: NEWCAS

In this paper, we present the design of 2 PLL for low power Bluetooth applications, one in 130nm PDSOI and the other in 28nm FDSOI technologies. The PDSOI one is based on a classical LC tank VCO and uses the possibility of body contact to modulate th

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::9df03f5d549bfa7dc6cec38037104caf
https://doi.org/10.1109/newcas.2014.6934072

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