A 28nm FD-SOI Standard Cell 0.6-1.2V Open-Loop Frequency Multiplier for Low Power SoC Clocking

Autor: Martin Cochet, Jean-Luc Autran, Pierre Schamberger, Damien Croain, Philipe Roche, Mehdi Naceur, Sylvain Clerc

Publikováno v: 2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2016, Unknown, Unknown Region. pp.1206-1209
ISCAS

IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, CANADA, MAY 22-25, 2016; International audience; This paper presents a new design for SoC clocking based on open-loop frequency multiplication. The architecture, fully implemente

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b7ebb358cf4bf76ad3de4d2c27366343
https://hal.archives-ouvertes.fr/hal-01434957