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Autor:
Donald W. Plass, Rajiv V. Joshi, Timothy J. Charest, Rolf Sautter, Daniel Rodko, R. Freese, Philip George Shephard, Y.-H. Chan, Tobias Werner, Pradip Patel, Uma Srinivasan, William V. Huott
Publikováno v:
2006 IEEE international SOI Conferencee Proceedings.
An embedded CMOS static random access memory (SRAM), including the array and a method of accessing cells in the array with improved cell stability for scalability and performance (over 5 GHz) is demonstrated in hardware using 65 nm Partially Depleted