Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip

Autor: Jongsun Park, Phi-Hung Pham, Junyoung Song, Chulwoo Kim

Publikováno v: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 21:173-177

This paper presents the silicon-proven design of a novel on-chip network to support guaranteed traffic permutation in multiprocessor system-on-chip applications. The proposed network employs a pipelined circuit-switching approach combined with a dyna

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::5f73a3914211cf62460baf8bbfb8a014
https://doi.org/10.1109/tvlsi.2011.2181545

Design and Implementation of Backtracking Wave-Pipeline Switch to Support Guaranteed Throughput in Network-on-Chip

Autor: Phuong Mau, Chulwoo Kim, Jongsun Park, Phi-Hung Pham

Publikováno v: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20:270-283

It is a challenging task in a network-on-chip to design an on-chip switch/router to dynamically support (hard) guaranteed throughput under very tight on-chip constraints of power, timing, area, and time-to-market. This paper presents the design and i

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::ee35d5b2243b9dde0594a7083a4948c1
https://doi.org/10.1109/tvlsi.2010.2096520

NeuFlow: Dataflow vision processing system-on-a-chip

Autor: Yann LeCun, Phi-Hung Pham, Darko Jelaca, Eugenio Culurciello, Clement Farabet, Berin Martini

Publikováno v: MWSCAS

This paper presents a bio-inspired vision system-on-a-chip - neuFlow SoC implemented in the IBM 45 nm SOI process. The neuFlow SoC was designed to accelerate neural networks and other complex vision algorithms based on large numbers of convolutions a

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::9c403d31563231f1ce14389784df3f1a
https://doi.org/10.1109/mwscas.2012.6292202

A low-power programmable DLL-based clock generator with wide-range anti-harmonic lock

Autor: Phi-Hung Pham, Yongtae Kim, Woonhyung Heo, Jabeom Koo

Publikováno v: 2009 International SoC Design Conference (ISOCC).

A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.13um CMOS technology. The proposed clock generator can generate a wide-range of the multiplied clock signals ranging from 125MHz to 2GHz. In addit

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::4a11fad559c96cde1ce616e5a4b15ab0
https://doi.org/10.1109/socdc.2009.5423833

Analysis and evaluation of traffic-performance in a backtracked routing network-on-chip

Autor: Chulwoo Kim, Phi-Hung Pham, Xuan-Tu Tran, P.T. Hong

Publikováno v: Second International Conference on Communications and Electronics, 2008. ICCE 2008.
Communications and Electronics, 2008. ICCE 2008. Second International Conference on
Communications and Electronics, 2008. ICCE 2008. Second International Conference on, Jun 2008, Hoian, Vietnam. pp.13-17, ⟨10.1109/CCE.2008.4578925⟩
Scopus-Elsevier

International audience; VLSI designers recently have adopted micro network-on-chip (or NoC) as an emerged solution to design complex SoC system under stringent constraints pertaining cost, size, power consumption, and short time-to-market. Characteri

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::cb495edcb70305977bc3730d5f26202e
https://doi.org/10.1109/cce.2008.4578925