Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Phaneendra Bikkina"'
Autor:
Lawrence T. Clark, Clifford S. Young-Sciortino, Steven M. Guertin, William E Brown, Keith E Holbert, Phaneendra Bikkina, Sumukh Bhanushali, Andrew Levy, Marek Turowski, Jim D. Butler
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 23:162-171
Autor:
Lawrence T. Clark, William E. Brown, Clifford S. Young-Sciortino, Jim D. Butler, Steven M. Guertin, Keith E. Holbert, Phaneendra Bikkina, Sumukh Bhanushali, Marek Turowski, Andrew Levy
Publikováno v:
IEEE Transactions on Nuclear Science. 69:2305-2313
Publikováno v:
ISCAS
This paper presents a 6-bit 20 GS/s 2-way time-interleaved (TI) flash analog-to-digital converter (ADC) in a 28-nm FDSOI CMOS technology. Leveraging threshold voltage control via back-gate bias in FDSOI, an automatic comparator offset calibration sch
Publikováno v:
2020 IEEE Texas Symposium on Wireless and Microwave Circuits and Systems (WMCS).
This paper presents a low-power 5 GS/s 6-bit flash analog-to-digital converter (ADC) fabricated in a 28-nm FDSOI CMOS technology for RF wideband radio receiver and high-speed serial link applications. The flash ADC leverages a 2-stage multi-bit searc
Autor:
Phaneendra Bikkina, Jeffrey Chen, Jinghong Chen, Runxi Zhang, Qingjun Fan, Yulang Feng, Hao Deng
Publikováno v:
LASCAS
This paper presents an automatic comparator offset calibration scheme for designing high-speed flash analog-to-digital data converters (ADCs). It leverages the threshold voltage control capability via back-gate in FDSOI CMOS technology and thus does
Publikováno v:
Analog Integrated Circuits and Signal Processing. 94:357-367
This paper proposes a feedback time difference amplifier (FTDA) that achieves linear, controllable gain and changeable input range for different time difference gains. The proposed FTDA consists of two identical feedback output generators. The feedba
Publikováno v:
ESSCIRC
This paper presents a 500 MS/s 10-bit single-channel SAR ADC with a reconfigurable double-rate comparator for enhanced operation speed. The proposed double-rate comparator effectively eliminates the delay caused by comparator reset from the critical
Autor:
Ashwath Hegde, Andrew Levy, Yu Long, Phaneendra Bikkina, Esko Mikkola, Alexander Odishvili, Jennifer Kitchen
Publikováno v:
Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018).
A radiation-hard, compact, low-mass, hybrid GaN and CMOS integrated module DC-DC converter has been designed with an input voltage of up to 14V regulated down to an output voltage of 1.5V, with 6A maximum load current. The converter exhibits greater
Publikováno v:
IGARSS
We present a low power radio frequency interference (RFI) mitigating receiver back-end application specific integrated circuit (ASIC). The ASIC includes an on-chip analog to digital converter (ADC) and a RFI detecting/mitigating digital signal proces
Publikováno v:
2016 IEEE Dallas Circuits and Systems Conference (DCAS).
This paper describes a feedback time difference amplifier (FTDA) with good linearity and high gain for coarse-fine time-to-digital converters. The symmetrical FTDA has two identical output generators. Each one consists of one SR-latch, one XOR gate,