Zobrazeno 1 - 10
of 15
pro vyhledávání: '"Peter Yiannacouras"'
Autor:
Deshanand Singh, Peter Yiannacouras
Publikováno v:
FPGAs for Software Programmers ISBN: 9783319264066
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::839392d7048f1de0597c90e478e137ca
https://doi.org/10.1007/978-3-319-26408-0_6
https://doi.org/10.1007/978-3-319-26408-0_6
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20:1429-1442
Field-programmable gate arrays (FPGAs) are increasingly used to implement embedded digital systems, however, the hardware design necessary to do so is time-consuming and tedious. The amount of hardware design can be reduced by employing a microproces
Publikováno v:
ACM Transactions on Reconfigurable Technology and Systems. 1:1-15
Advancements in reconfigurable technologies, specifically FPGAs, have yielded faster, more power-efficient reconfigurable devices with enormous capacities. In our work, we provide testament to the impressive capacity of recent FPGAs by hosting a comp
Publikováno v:
ACM SIGARCH Computer Architecture News. 35:9-19
Embedded systems designers that use FPGAs are increasingly including soft processors in their designs (configurable processors built in the programmable logic of the FPGA). While there has been a significant amount of research on adding custom instru
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 26:266-277
As embedded systems designers increasingly use field-programmable gate arrays (FPGAs) while pursuing single-chip designs, they are motivated to have their designs also include soft processors, processors built using FPGA programmable logic. In this p
Autor:
David Neto, Tomasz Czajkowski, Utku Aydonat, John Freeman, Jason Wong, Michael Kinsner, Dmitry N. Denisenko, Peter Yiannacouras, Deshanand Singh
Publikováno v:
FPL
We present an OpenCL compilation framework to generate high-performance hardware for FPGAs. For an OpenCL application comprising a host program and a set of kernels, it compiles the host program, generates Verilog HDL for each kernel, compiles the ci
Publikováno v:
CASES
Embedded systems are often implemented on FPGA devices and 25% of the time include a soft processor--a processor built using the FPGA reprogrammable fabric. Because of their prevalence and flexibility, soft processors are compelling targets for custo
Publikováno v:
FPL
Commercial soft processors are unable to effectively exploit the data parallelism present in many embedded systems workloads, requiring FPGA designers to exploit it (laboriously) with manual hardware design. Recent research [1, 2] has demonstrated th
Publikováno v:
FPGA
Soft processors are often used in FPGA-based systems because of their ease-of-use, but for a given computation there is a significant gap in area/performance between a C code implementation executing on a soft processor and a custom FPGA hardware imp
Publikováno v:
CASES
While soft processors are increasingly common in FPGA-based embedded systems, it remains a challenge to scale their performance. We propose extending soft processor instruction sets to include support for vector processing. The resulting system of ve