Zobrazeno 1 - 10
of 23
pro vyhledávání: '"Peter Teske"'
Autor:
Daniel Cardoso de Carvalho, Denise Aparecida Andrade de Oliveira, José Enemir dos Santos, Peter Teske, Luciano B. Beheregaray, Horacio Schneider, Iracilda Sampaio
Publikováno v:
Genetics and Molecular Biology, Vol 32, Iss 3, Pp 601-607 (2009)
A molecular phylogenetic analysis based on mitochondrial 16S ribosomal DNA and Control Region sequences from native and introduced populations was undertaken, in order to characterize the introduction of Cichla (peacock bass or tucunaré) species in
Externí odkaz:
https://doaj.org/article/c19cd8fc3afd4e4d804059cdd0bf23ca
Publikováno v:
South African Journal of Science, Vol 107, Iss 5/6 (2011)
The southern African marine realm is located at the transition zone between the Atlantic and Indo-Pacific biomes. Its biodiversity is particularly rich and comprises faunal and floral elements from the two major oceanic regions, as well as a large nu
Externí odkaz:
https://doaj.org/article/f9de5f8cb6ab42c6aa638910ad2f1e1d
Publikováno v:
IEEE Journal of Emerging and Selected Topics in Power Electronics. 10:7049-7061
Publikováno v:
IEEE Journal of Emerging and Selected Topics in Power Electronics. 9:7422-7435
This paper deals with the harmonic resonance investigation of modern converter dominated power systems considering asymmetric operation conditions. Initially, the complex domain harmonic transfer matrix (HTM) models for the grid-following voltage sou
Publikováno v:
2022 IEEE 13th International Symposium on Power Electronics for Distributed Generation Systems (PEDG).
Publikováno v:
2022 IEEE 13th International Symposium on Power Electronics for Distributed Generation Systems (PEDG).
Publikováno v:
2021 6th IEEE Workshop on the Electronic Grid (eGRID).
Publikováno v:
2020 IEEE 21st Workshop on Control and Modeling for Power Electronics (COMPEL).
Reliable grid voltage angle detection by Phase-Locked Loops (PLL) is crucial for grid converter control to accurately inject power and quickly respond to grid faults, e.g., during Fault Ride-Through (FRT). The design of PLLs is typically based on sim