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Autor:
Glenn Peter Giacalone, S. Divakaruni, Peter Joel Jenkins, John A. Fifield, M. Hodges, Jeffrey S. Zimmerman, Robert E. Busch, A. Davidovich, M. Vincent, M. Kozyrczak, Christopher P. Miller, Wayne J. Howell, C. Reed, F. Creed, Thomas E. Obremski, Charles Edward Drake, T. von Reyn, G. Rohrbaugh, C. Ematrudo
Publikováno v:
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.
Several cache-DRAMs have been reported, but all require multiple chips to implement an L2 cache system. The advent of 20 ns, 16 Mb DRAM technology has made a high-speed single-chip 1MB cache possible, replacing multiple SRAM and logic modules, saving
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dc4f3df86c68ee4b283ada19fb890d82
https://doi.org/10.1109/isscc.1996.488721
https://doi.org/10.1109/isscc.1996.488721
