Zobrazeno 1 - 10
of 21
pro vyhledávání: '"Peter E. Cottrell"'
Autor:
J.-E. Mueller, Ralf Brederlow, H.S. Bennett, Peter E. Cottrell, J.C. Costa, M. Racanelli, W.M. Huang, A.A. Immorlica, Bin Zhao, Hisashi Shichijo, C.E. Weitzel
Publikováno v:
IEEE Transactions on Electron Devices. 52:1235-1258
The relationships between device feature size and device performance figures of merit (FoMs) are more complex for radio frequency (RF) applications than for digital applications. Using the devices in the key circuit blocks for typical RF transceivers
Autor:
M. I. Younus, Michael J. Hauser, Rebecca D. Mih, D. Hoyniak, J. M. Johnson, Matthew J. Breitwisch, W. G. Crocco, Peter E. Cottrell, Wagdi W. Abadeer, A. Moriwaki, Terence B. Hook, E. Phipps, J. Rivard, Orest Bula, Beth Ann Rainey, Randy W. Mann, Jeffrey S. Brown, Christopher S. Putnam, Chung Hon Lam, J. Toomey, Stephen S. Furkay, Bryant C. Colwill
Publikováno v:
IBM Journal of Research and Development. 47:553-566
An ultralow-standby-power technology has been developed in both 0.18-µm and 0.13-µm lithography nodes for embedded and standalone SRAM applications. The ultralow-leakage six-transistor (6T) SRAM cell sizes are 4.81 µm2 and 2.34 µm2, corre
Autor:
Terence B. Hook, Jeffrey S. Brown, Randy W. Mann, Eric Adler, D. Hoyniak, J. Johnson, Peter E. Cottrell
Publikováno v:
IEEE Transactions on Electron Devices. 50:1946-1951
Lateral scattering of retrograde well implants is shown to have an effect on the threshold voltage of nearby devices. The threshold voltage of both NMOSFETs and PMOSFETs increases in magnitude for conventional retrograde wells, but for triple-well is
Publikováno v:
IBM Journal of Research and Development. 44:142-156
The FIELDAY program simulates semiconductor devices of arbitrary shape in one, two, or three dimensions operating under transient or steady-state conditions. A wide variety of physical effects, important in bipolar and field-effect transistors, can b
Autor:
Jeffrey S. Brown, Peter E. Cottrell, Matthew J. Breitwisch, Terence B. Hook, Randy W. Mann, Chung H. Lam, D. Hoyniak
Publikováno v:
IEEE Transactions on Electron Devices. 49:1499-1501
Various aspects of ultra-low leakage static random-access memories (SRAM) cell design are considered. It is shown that the high threshold voltage relative to the power supply so improves the stability of the cell that the beta ratio of the design may
Autor:
Julio C. Costa, W.M. Huang, Bin Zhao, Charles E. Weitzel, J.-E. Mueller, H.S. Bennett, M. Racanelli, A.A. Immorlica, Hisashi Shichijo, Peter E. Cottrell
Publikováno v:
2006 Bipolar/BiCMOS Circuits and Technology Meeting.
The International Technology Roadmap for Semiconductor (ITRS) Radio Frequency and Analog/Mixed-Signal (RF and AMS) Wireless Technology Working Group (TWG) addresses device technologies for wireless communications covering both silicon and III-V compo
Autor:
J.-E. Mueller, M. Racanelli, W.M. Huang, A.A. Immorlica, J.C. Costa, Peter E. Cottrell, Bin Zhao, H.S. Bennett, H. Shichijo, Charles E. Weitzel
Publikováno v:
2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.
Radio frequency (RF) and analog/mixed-signal (AMS) integrated circuits (ICs) are key enabling components for mobile and wireless communications and their advancements continue to drive the growth of the related semiconductor market. The circuit and t
Autor:
Merritt Funk, Qingyun Yang, Joyce C. Liu, Matthew Sendelbach, Jeffrey S. Brown, Daniel J. Prager, Peter E. Cottrell, David V. Horak, Eric P. Solecky, Randy W. Mann, Sadanand V. Deshpande, Wesley C. Natzle, F. Higuchi, Chienfan Yu, Hussein I. Hanafi, Akihisa Sekiguchi, Subramanian S. Iyer, W. Yan, Bruce B. Doris, Masayuki Tomoyasu, James P. Norum, Len Y. Tsou, Asao Yamashita, Hiroyuki Takahashi
Publikováno v:
2004 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (IEEE Cat. No.04CH37530).
A method for formation and control of silicon gates or fins uses trim of a hard mask by a new gaseous oxide etch. The method decouples final feature size from lithography and from the RIE resist trim/oxide mask open processes. Logic blocks with two s
Autor:
Alan J. Weger, Peilin Song, Peter E. Cottrell, Franco Stellari, Mujahid Muhammad, Kiran V. Chatty, Moyra K. McManus, Robert J. Gauthier
Publikováno v:
2004 IEEE International Reliability Physics Symposium. Proceedings.
An analytical model has been developed to provide physical design guidelines to suppress CDE-induced latchup in CMOS ICs. The design guidelines implemented in two test chips in IBM's 130nm technology successfully suppressed latchup against transient
Autor:
P. Saunders, David M. Fried, Diane C. Boyd, J. Kedzierski, Edward J. Nowak, A.P. Johnson, Thomas S. Kanarsky, Chienfan Yu, D. Rakowski, J. Newbury, N. Carpenter, S.P. Cole, Hussein I. Hanafi, H.E. Young, Jed H. Rankin, C.P. Willets, Qingyun Yang, Peter E. Cottrell, Ying Zhang, Wesley C. Natzle, Hon-Sum P. Wong, Ronnen Andrew Roy, Beth Ann Rainey, Meikei Ieong
Publikováno v:
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).
Double-gate FinFET devices with asymmetric and symmetric polysilicon gates have been fabricated. Symmetric gate devices show drain currents competitive with fully optimized bulk silicon technologies. Asymmetric-gate devices show |V/sub t/|/spl sim/0.