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pro vyhledávání: '"Peter C. S. Scholtens"'
Publikováno v:
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This paper focuses on several methods to save power consumption in mismatch limited ADC designs, like flash and folding architectures. Migrating existing designs to a next submicron technology helps to reduce the power consumption significantly. It i
Publikováno v:
Proceedings of the 30th European Solid-State Circuits Conference.
Key device parameters such as drain current, transconductance, current factor, capacitance, etc. are linked to typical analog circuit level performance criteria, as a function of the CMOS technology node. Subsequently, speed and power implications fo
Publikováno v:
Proceedings of the 30th European Solid-State Circuits Conference.
A 1.6 GS/s track and hold circuit that produces 16 interleaving, 100 MS/s voltage buffered output signals is presented. The achieved SFDR for a 950 MHz full scale input signal is 50 dB. Phase alignment is better than 2 ps and aperture uncertainty is
Publikováno v:
Analog Circuit Design ISBN: 9780792376217
The impact of scaling on the analog performance of MOS circuits was studied. The solution space for analog scaling was explored between two dimensions: a “standard digital scaling” axis and an “increased bandwidth and dynamic-range” axis. Cir
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::96fe5e4fed6d1fbdbedfa8aca51d56c0
https://doi.org/10.1007/0-306-47950-8_1
https://doi.org/10.1007/0-306-47950-8_1