Zobrazeno 1 - 10
of 185
pro vyhledávání: '"Peter A. Beerel"'
Autor:
Gourav Datta, Souvik Kundu, Zihan Yin, Ravi Teja Lakkireddy, Joe Mathai, Ajey P. Jacob, Peter A. Beerel, Akhilesh R. Jaiswal
Publikováno v:
Scientific Reports, Vol 12, Iss 1, Pp 1-16 (2022)
Abstract The demand to process vast amounts of data generated from state-of-the-art high resolution cameras has motivated novel energy-efficient on-device AI solutions. Visual data in such cameras are usually captured in analog voltages by a sensor p
Externí odkaz:
https://doaj.org/article/eee7c4ebf07a4b1bac052f4567cc4578
Autor:
Md Abdullah-Al Kaiser, Gourav Datta, Zixu Wang, Ajey P. Jacob, Peter A. Beerel, Akhilesh R. Jaiswal
Publikováno v:
Frontiers in Neuroinformatics, Vol 17 (2023)
Edge devices equipped with computer vision must deal with vast amounts of sensory data with limited computing resources. Hence, researchers have been exploring different energy-efficient solutions such as near-sensor, in-sensor, and in-pixel processi
Externí odkaz:
https://doaj.org/article/1c37198107ae459e8c5f276fce19c842
Publikováno v:
Frontiers in Neuroscience, Vol 16 (2022)
High-quality 3D image recognition is an important component of many vision and robotics systems. However, the accurate processing of these images requires the use of compute-expensive 3D Convolutional Neural Networks (CNNs). To address this challenge
Externí odkaz:
https://doaj.org/article/d34f9de400bf48ee8817a31afcd0808a
Publikováno v:
ACM Transactions on Embedded Computing Systems. 21:1-24
We present a dynamic network rewiring (DNR) method to generate pruned deep neural network (DNN) models that both are robust against adversarially generated images and maintain high accuracy on clean images. In particular, the disclosed DNR training m
Publikováno v:
Proceedings of the Great Lakes Symposium on VLSI 2023.
In this paper, we describe and analyze an island-based random dynamic voltage scaling (iRDVS) approach to thwart power side-channel attacks. We first analyze the impact of the number of independent voltage islands on the resulting signal-to-noise rat
Autor:
Md Abdullah-Al Kaiser, Gourav Datta, Sreetama Sarkar, Souvik Kundu, Zihan Yin, Manas Garg, Ajey P. Jacob, Peter A. Beerel, Akhilesh R. Jaiswal
Publikováno v:
Proceedings of the Great Lakes Symposium on VLSI 2023.
The massive amounts of data generated by camera sensors motivate data processing inside pixel arrays, i.e., at the extreme-edge. Several critical developments have fueled recent interest in the processing-in-pixel-in-memory paradigm for a wide range
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41:979-992
Latches have the advantages of timing-borrowing, smaller cell area, lower input capacitance, and lower power compared to flip-flops (FFs). This paper presents a CAD flow that converts any arbitrarily complex single-clock-domain FF-based RTL design in
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783031250743
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1430c8aa8b2b929bb6eb8d5398e0c004
https://doi.org/10.1007/978-3-031-25075-0_22
https://doi.org/10.1007/978-3-031-25075-0_22
Publikováno v:
2023 IEEE/CVF Winter Conference on Applications of Computer Vision (WACV).
Publikováno v:
ACM Transactions on Design Automation of Electronic Systems. 26:1-17
Single flux quantum (SFQ) logic is a promising technology to replace complementary metal-oxide-semiconductor logic for future exa-scale supercomputing but requires the development of reliable EDA tools that are tailored to the unique characteristics