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Akademický článek
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Autor:
Jonathan L. Holland, Stephen Knol, Li Sun, Sam Yang, Hai Dang, John Jianhong Zhu, Bo Yu, Reza Jalilizeinali, Xiaohua Kong, Chiew-Guan Tan, Alvin Leng Sun Loke, Lixin Ge, Tin Tin Wee, Zhiqin Chen, Da Yang, Kumar Albert, Kern Rim, Jun Yuan, Burton M. Leary, Wilson Jianbo Chen, Sreeker Dundigal, Deqiang Song, Chulkyu Lee, Steven James Dillen, Patrick G. Drennan, Esin Terzioglu, Stanley Seungchul Song, Hasnain Lakdawala, Periannan Chidambaram, Jihong Choi
Publikováno v:
Hybrid ADCs, Smart Sensors for the IoT, and Sub-1V & Advanced Node Analog Circuit Design ISBN: 9783319612843
Consumer demand for low-power mobile ICs has propelled CMOS scaling to arrive at the fully depleted finFET with foundry offerings already available at 16/14, 10, and 7 nm. The compact three-dimensional structure of the finFET offers superior short-ch
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6f9a93acedd44b3f7899ad05e8d60143
https://doi.org/10.1007/978-3-319-61285-0_14
https://doi.org/10.1007/978-3-319-61285-0_14
Autor:
Da Yang, Geoffrey Yeap, Periannan Chidambaram, Giri Nallapadi, S. C. Song, Chock H. Gan, John Jianhong Zhu, Jeff Xu
Publikováno v:
SPIE Proceedings.
How to maintain the Moore’s Law scaling beyond the 193 immersion resolution limit is the key question semiconductor industry needs to answer in the near future. Process complexity will undoubtfully increase for 14nm node and beyond, which brings bo