Zobrazeno 1 - 10
of 43
pro vyhledávání: '"Pei Siang Lim"'
Autor:
Sharon Pei Siang Lim, Ser Choong Chong, Wen Wei Seit, Jacob Jordan Soh, Sasi Kumar Tippabhotla, Vempati Srinivasa Rao
Publikováno v:
2022 IEEE 24th Electronics Packaging Technology Conference (EPTC).
Publikováno v:
2022 IEEE 24th Electronics Packaging Technology Conference (EPTC).
Publikováno v:
2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).
Autor:
Sharon Pei Siang Lim, Ser Choong Chong, David Ho Soon Wee, Wen Wei Seit, Jacob Jordan Soh, Tai Chong Chai
Publikováno v:
2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC).
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
As the industry for 2.5D and 3D technology moving towards higher interconnect density and faster performance with tighter bump pitch at $\mathrm{20}\mu\mathrm{m}$ and below, there is a need to search and study a different bonding options and technolo
Autor:
Yosephine Andriani, Xiaobai Wang, Simon Siak Boon Lim, Xiaowu Zhang, Boon Long Lau, Yong Han, Ming Chinq Jong, Haoran Chen, Songlin Liu, Sharon Pei Siang Lim
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
In this paper, we present the design and fabrication of a mold-1st FOWLP that seeks to solve potential warpage and reliability issues. We examined three different mold-1st FOWLP options that are designed and developed for this work. We have created v
Autor:
Norhanani Binte Jaafar, Tai Chong Chai, Ser Choong Chong, Sharon Pei Siang Lim, Sharon Seow Huang Lim
Publikováno v:
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC).
The Fan-out wafer-level packaging technology is an integrated circuit technology as well as an enhancement of standard wafer-level packaging (WLP) solutions. This technology is an attractive packaging approach for mobile applications and heterogeneou
Autor:
Xiaobai Wang, Songlin Liu, Sharon Pei Siang Lim, Ming Chinq Jong, Yong Han, Simon Siak Boon Lim, Haoran Chen, Yosephine Andriani, Xiaowu Zhang, Boon Long Lau
Publikováno v:
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC).
This paper presents a comprehensive board level solder joint reliability study under thermal cycling (TC) loading by both numerical simulation and experimental test. TC profile is from −40°C to 125°C. In numerical simulation, both epoxy molding c
Publikováno v:
2019 IEEE 21st Electronics Packaging Technology Conference (EPTC).
Ultrathin die pick-up is studied for 3D IC applications. Failure modes are identified as follows: 1) no pick-up due to insufficient peeling; 2) die crack created by ejector; 3) neighboring die crack due to ejector push-up. Optimal dicing tape is sele
Autor:
Ming Chinq Jong, Simon Siak Boon Lim, Boon Long Lau, Sharon Pei Siang Lim, Xiaowu Zhang, Calvin Hung Ming Chua, Lin Bu
Publikováno v:
2019 IEEE 21st Electronics Packaging Technology Conference (EPTC).
In semiconductor industry, it is very attractive to develop cracking free RDL, low warpage and high solder joint reliability FOWLP. Solder joint reliability is a big issue and can lead to interconnect failure, which is related to package design, mate