A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction.

Autor: Setterberg, Brian, Poulton, Ken, Ray, Sourja, Huber, Dan J., Abramzon, Valentin, Steinbach, Guenter, Keane, John P., Wuppermann, Bernd, Clayson, Mathew, Martin, Matthew, Pasha, Rizwan, Peeters, Edda, Jacobs, Annemie, Demarsin, Filip, Al-Adnani, Adnan, Brandt, Peter

Publikováno v: 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers; 2013, p466-467, 2p