Zobrazeno 1 - 2
of 2
pro vyhledávání: '"Pawel Ządek"'
Publikováno v:
IFAC-PapersOnLine. 48:186-192
The paper presents a new approach to improve efficiency of the verification process through acceleration of tests. The verification eco-system based on well-accepted industry standards, consisting of essential functionality and an emulation platform
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::38e9bff53d6eb68131c7a34630e65e1c
https://doi.org/10.1016/j.ifacol.2015.07.030
https://doi.org/10.1016/j.ifacol.2015.07.030
Publikováno v:
IFAC-PapersOnLine. 48:180-185
The paper presents techniques being developed in order to improve verification efficiency in the FPGA-in-the-Loop environment. The verification speed-up in relation to typical software simulation within MATLAB® suite offered to the presented verific
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::03fe17b796c236f47c05a58cdd54e8fa
https://doi.org/10.1016/j.ifacol.2015.07.029
https://doi.org/10.1016/j.ifacol.2015.07.029