Zobrazeno 1 - 10
of 29
pro vyhledávání: '"Paul-Chang Lin"'
Autor:
Yi Yang, Xuan-Jie Liu, Peng He, Xiao-Jun Chen, Ri-hui Sun, Paul-Chang Lin, Jian-Yong Jiang, Guang-Ning Li
Publikováno v:
ECS Transactions. 52:443-451
TSV (Through Silicon Via) is a new method for 3D technology (IC integration). Different chips can be connected with the Cu line through silicon substrate. Via area is so deep (usually 100-300um) that we need thicker barrier and seed layer. The Cu pla
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3339eb08d1c3dffe5ed26ebfadfa50d8
https://doi.org/10.1149/05201.0443ecst
https://doi.org/10.1149/05201.0443ecst
Publikováno v:
ECS Transactions. 44:505-509
Self Ionized Plasma (SIP) Ti/TiN Process is used for barrier and glue layer before tungsten deposition in backend-of-the-line (BEOL). Long Throw technology and AC Bias are applied to gain better step coverage. But wafer backside arcing case happened
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3ea56b21497d254cefb2f556c3d5dd5a
https://doi.org/10.1149/1.3694361
https://doi.org/10.1149/1.3694361
Publikováno v:
ECS Transactions. 44:737-743
Hillock is formed at the film surface in Cu metallization process. During the growth of hillock, the tensile stress built in the copper (Cu) metal film due to the relieved thermal expansion coefficients. These "hillocks" are just areas of localized c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b417dad472f45606a84f70f7d31e30f0
https://doi.org/10.1149/1.3694392
https://doi.org/10.1149/1.3694392
Publikováno v:
ECS Transactions. 44:745-749
Via bottom void is one of the problems related to the metal interconnections in semiconductor devices. In 0.13μm technology, Novellus Sabre serial is wildly applied as copper(Cu) electro chemical plating (ECP) tool, but the problem of high hit ratio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2dd4cda46b8a4cee3b0db374e949db57
https://doi.org/10.1149/1.3694393
https://doi.org/10.1149/1.3694393
Publikováno v:
ECS Transactions. 44:791-796
MIM is the three words of metal insulator metal. This structure is always designed into IC device and act as a big capacitor to keep the stable working voltage. In MIM loop, the upper capacitor board is made of thin Al film. Because of this character
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f1e9f994e811db0a7ffff0ab7a2288af
https://doi.org/10.1149/1.3694400
https://doi.org/10.1149/1.3694400
Publikováno v:
ECS Transactions. 44:471-476
ILB (Integration liner barrier) is the combination of IMP (Ionic Metal Plasma) Ti and MOCVD (Metal-Organic-Chemical-Vapor-Deposition) TiN, which is widely employed in semiconductor manufacturing as a tungsten glue/barrier layer. Contact resistance is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6df608fe5818cc07e996f1a8fe16e829
https://doi.org/10.1149/1.3694355
https://doi.org/10.1149/1.3694355
Autor:
Jin-Hai Xu, Tony Zhu, Paul-Chang Lin, Keliang Pang, Danny Chen, Yuchun Wang, Pei Li, Xucheng Wang, Zhiyong Ma
Publikováno v:
ECS Transactions. 44:537-542
3D integration utilizing TSV (Through-Silicon Via) is a promising technology to achieve high performance 3DIC (three-dimentional integrated circuit), not only because it exponentially increases connection efficiency between dies, but also because it
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::37c60bfe2d7a687a474b39ca50578fc1
https://doi.org/10.1149/1.3694366
https://doi.org/10.1149/1.3694366
Autor:
Ri-Hui Sun, Charles Xing, Yi Yang, Paul-Chang Lin, Xiao-Chun Kang, Dong-Yi Zhou, Jian-Yong Jiang, Peng He
Publikováno v:
ECS Transactions. 44:797-801
Copper (Cu) material is being widely used in the advance ultra large-scale integration (ULSI) in the metallization process due to its low resistivity and good performance on EM in 130nm and below technology node. In Cu metallization process of 130nm,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::58c546ecd8e6195b980094a61f72c96e
https://doi.org/10.1149/1.3694401
https://doi.org/10.1149/1.3694401
Publikováno v:
ECS Transactions. 34:677-681
Copper has been used as inter-wiring in deep-submicron integrated circuit (IC) for its lower resistivity and potentially higher resistance to electro migration. Copper Chemical-mechanical polishing/planarization (Cu CMP) is used to remove the redunda
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6d4a6751e07f2222353effe146947644
https://doi.org/10.1149/1.3567657
https://doi.org/10.1149/1.3567657
Publikováno v:
ECS Transactions. 34:743-748
Shallow Trench Isolation(STI) is widely used in advanced CMOS technologies. This paper describes a shallow trench isolation for 0.13μm CMOS technologies development which utilizes AMAT Ultima Plus High Density Plasma (HDP) CVD oxide process to fill
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::982a57562833474645aad8d79a8dd246
https://doi.org/10.1149/1.3567667
https://doi.org/10.1149/1.3567667