Zobrazeno 1 - 10
of 21
pro vyhledávání: '"Paul S. McLaughlin"'
Autor:
Xunyuan Zhang, B. Peethala, Takeshi Nogami, James J. Demarest, O. van der Straten, Xiaoxuan Sun, Chao-Kun Hu, Xuan Lin, Marinus Hopstaken, Motoyama Koichi, James J. Kelly, Paul S. McLaughlin
Publikováno v:
ECS Transactions. 80:297-309
CVD Co liners are of interest for back end of the line (BEOL) interconnects due to improved Cu interconnect gapfill, especially at narrow feature widths.1-4 The stability of Co liner during downstream BEOL processing is a concern that has been discus
Autor:
Lynne Gignac, Hosadurga Shobha, Paul S. McLaughlin, M. Ali, Chao-Kun Hu, James J. Demarest, C. M. Breslin, Y. Ostrovski, G. Lian, J. Benedict, X.-H. Liu, Jiamin Ni, Cyril Cabral, Motoyama Koichi
Publikováno v:
2018 IEEE International Electron Devices Meeting (IEDM).
Mechanisms of electromigration (EM) damage in Cu interconnects through various CMOS nodes are reviewed. Pure Cu and Cu alloy interconnects that were used down to 14 nm node can no longer satisfy the electrical current used for 10 nm node and beyond i
Autor:
Paul S. McLaughlin, Thomas J. Haigh, Devika Sil, Huai Huang, Nicholas A. Lanzillo, Raghuveer R. Patlolla, Pranita Kerber, Hosadurga Shobha, James Chingwei Li, C. B. Pcethala, Yongan Xu, Donald F. Canaperi, James J. Demarest, Elbert E. Huang, Chanro Park, Clevenger Leigh Anne H, Benjamin D. Briggs, Licausi Nicholas, Jae Gon Lee, M. Ali, Son Nguyen, Young-Wug Kim, Theodorus E. Standaert, C. T. Le, G. Lian, Griselda Bonilla, Errol Todd Ryan, Han You, David L. Rath
Publikováno v:
2018 IEEE International Interconnect Technology Conference (IITC).
As BEOL pitch continues to aggressively scale, contributions from pattern dimension and edge placement constrict the available geometry of interconnects. In particular, the critical minimum insulator spacing which defines a technologies max operating
Autor:
Yongan Xu, Peethala Cornelius Brown, Hosadurga Shobha, Chanro Park, Huai Huang, Devika Sil, Pranita Kerber, Raghuveer R. Patlolla, David L. Rath, Clevenger Leigh Anne H, M. Ali, James Chingwei Li, Jae Gon Lee, Paul S. McLaughlin, Benjamin D. Briggs, Thomas J. Haigh, C. T. Le, G. Lian, Theodorus E. Standaert, Son Nguyen, Nicholas A. Lanzillo, Licausi Nicholas, Donald F. Canaperi, Elbert E. Huang, Errol Todd Ryan, Han You, Griselda Bonilla, James J. Demarest, Young-Wug Kim
Publikováno v:
2017 IEEE International Electron Devices Meeting (IEDM).
A fully aligned via (FAV) integration scheme is introduced and demonstrated at 36 nm metal pitch, with extendibility to beyond the 7 nm node. Selective chemistries were developed to recess Cu and W wires and their associated barrier liner materials,
Autor:
Donald F. Canaperi, Raghuveer R. Patlolla, Daniel C. Edelstein, Griselda Bonilla, Huai Huang, Wei Wang, E. Todd Ryan, Paul S. McLaughlin, Xunyuan Zhang, Juntao Li, Terry A. Spooner, Eric G. Liniger, Frank W. Mont, Chao-Kun Hu, C. Labelle
Publikováno v:
2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC).
48 nm pitch dual damascene interconnects are patterned and filled with ruthenium. Ru interconnect has comparable high yield for line and via macros. Electrical results show minimal impact for via resistance and around 2 times higher line resistance.
Autor:
Vamsi Paruchuri, Juntao Li, Takeshi Nogami, Daniel C. Edelstein, Terry A. Spooner, Stephan A. Cohen, Theodorus E. Standaert, Moosung M. Chae, James J. Kelly, Terence Kane, Donald F. Canaperi, Elbert E. Huang, Benjamin D. Briggs, Raghuveer R. Patlolla, Deepika Priyadarshini, Sevim Korkmaz, Paul S. McLaughlin, Christopher Parks, Christopher J. Penny, Anita Madan, Xunyuan Zhang, Hosadurga Shobha, Wei Wang, Son Nguyen, Thomas M. Shaw
Publikováno v:
2015 IEEE International Electron Devices Meeting (IEDM).
Through-Co self-forming-barrier (tCoSFB) metallization scheme is introduced, with Cu gap-fill capability down to 7 nm-node dimensions. Mn atoms from doped-seedlayer diffuse through CVD-Co wetting layer, to form TaMn O barrier, with integrity proven b
Autor:
Gregory G. Freeman, E. J. Nowak, L. Sigal, Daniel J. Poindexter, Narasimha Rao Mavilla, C-H. Lin, Mohit Bajaj, Suresh Gundapaneni, James D. Warnock, Steven W. Mittl, Richard A. Wachnik, C. Scott, Noah Zamdmer, Paul S. McLaughlin, Siyuranga O. Koswatta, Sungjae Lee, J. Johnson
Publikováno v:
2015 IEEE International Electron Devices Meeting (IEDM).
In this paper we show that devices in scaled technologies could undergo self-heating (SH) even in the off-state when subjected to stress conditions that would in turn adversely impact product life-time. We present a detailed methodology in analyzing
Autor:
Dileep N. Netrabile, Timothy D. Sullivan, Paul S. McLaughlin, Jeanne P. Bickford, Peter A. Habitz, Baozhen Li
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 11:86-91
Chip level electromigration (EM) reliability is determined by: 1) the element level EM failure probability used for design guideline generation; and 2) the distribution of EM elements against design limits. Balancing these two factors is critical for
Autor:
Clevenger Lawrence A, James J. Demarest, Kaushik Chanda, Birendra N. Agarwala, Chao-Kun Hu, Du B. Nguyen, Chih-Chao Yang, Paul S. McLaughlin, H. S. Rathore
Publikováno v:
ECS Transactions. 1:77-91
In the advanced on-chip interconnect Technology, the interconnect reliability has been a subject of utmost importance. As the line width is reduced to the sub -micron range, the current carrying capability of the Cu interconnect lines becomes an impo
Autor:
Baozhen Li, Xiao Hu Liu, Junjing Bao, Paul S. McLaughlin, R. G. Filippi, Ping-Chuan Wang, Lijuan Zhang
Publikováno v:
2013 IEEE International Reliability Physics Symposium (IRPS).
Electromigration lifetime and failure mechanism have been investigated for Cu/low-k interconnects at intermediate interconnect levels. It was observed that extrusion fails occurred mostly before resistance shift fails were detected. The activation en