Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Paul Racunas"'
Autor:
Michael B. Sullivan, Nirmal R. Saxena, Mike O'Connor, Donghyuk Lee, Paul Racunas, Saurabh Hukerikar, Timothy Tsai, Siva Kumar Sastry Hari, Stephen W. Keckler
Publikováno v:
IEEE Micro. 42:69-77
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::068076a486e60f30bc26fd2bd88bf0fb
https://doi.org/10.1109/mm.2022.3163122
https://doi.org/10.1109/mm.2022.3163122
Autor:
Michael J. Sullivan, Nirmal Saxena, Stephen W. Keckler, Mike O'Connor, Siva Kumar Sastry Hari, Saurabh Hukerikar, Paul Racunas, Timothy Tsai, Donghyuk Lee
Publikováno v:
MICRO
GPUs are used in high-reliability systems, including high-performance computers and autonomous vehicles. Because GPUs employ a high-bandwidth, wide-interface to DRAM and fetch each memory access from a single DRAM device, implementing full-device cor
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::11720616142d3d84858253ba6b9d3f31
https://doi.org/10.1145/3466752.3480111
https://doi.org/10.1145/3466752.3480111
Publikováno v:
ITC
Accurate determination of the safe-fault failure rate of complex digital designs is an exascale problem. We present a novel measurement methodology and results which could have a profound impact on the performance and availability for GPUs in safety
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::889c8d964f2f9ca39df4d9f8f20d7829
https://doi.org/10.1109/itc44778.2020.9325239
https://doi.org/10.1109/itc44778.2020.9325239
Autor:
Paul Racunas, Saurabh Hukerikar, Yanxiang Huang, Richard Bramley, Atieh Lotfi, Keshav Balasubramanian, Nirmal Saxena
Publikováno v:
ITC
Safety is the most important aspect of an autonomous driving platform. Deep neural networks (DNNs) play an increasingly critical role in localization, perception, and control in these systems. The object detection and classification inference are of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::65739e795b8f03286f5f0c5026512faf
https://doi.org/10.1109/itc44170.2019.9000150
https://doi.org/10.1109/itc44170.2019.9000150
Publikováno v:
DSN
Cache structures on modern GPUs or CPUs occupy a large area and are frequently accessed. This increases their vulnerability to transient errors. With some area and energy overhead, these structures are often protected by ECC or parity checking. Howev
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7daad84337074115e9c8b1f2c5182c50
https://doi.org/10.1109/dsn.2018.00041
https://doi.org/10.1109/dsn.2018.00041
Publikováno v:
MICRO
The rate of particle induced soft errors in a processor increases in proportion to the number of bits. This soft error rate (SER) can limit the performance of a system by placing an effective limit on the number of cores, nodes or clusters. The vulne
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::75dad1b87dbc153036a1678b43c27cc9
https://doi.org/10.1145/2830772.2830829
https://doi.org/10.1145/2830772.2830829
Publikováno v:
IEEE Computer Architecture Letters. 7:21-24
ACE (architecturally correct execution) analysis computes AVFs (architectural vulnerability factors) of hardware structures. AVF expresses the fraction of radiation-induced transient faults that result in user-visible errors. Architects usually perfo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ef95f517a54f146d222ea4ab9d63e593
https://doi.org/10.1109/l-ca.2007.19
https://doi.org/10.1109/l-ca.2007.19
Autor:
Ram Rangan, Shubhendu S. Mukherjee, Razvan Cheveresan, Paul Racunas, Arijit Biswas, Joel Emer
Publikováno v:
ISCA
Processor designers require estimates of the architectural vulnerability factor (AVF) of on-chip structures to make accurate soft error rate estimates. AVF is the fraction of faults from alpha particle and neutron strikes that result in user-visible
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::96c03f69c06f5e502160233aa2db1e01
https://doi.org/10.1109/isca.2005.18
https://doi.org/10.1109/isca.2005.18
Autor:
Yale N. Patt, Paul Racunas
Publikováno v:
ICS
The high clock frequencies of modern superscalar processors make the wire delay incurred in moving data across the processor chip a significant concern. As frequencies continue to increase, it will become more difficult for a centralized first level
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::00d780db039827cbeac473b56a70a67d
https://doi.org/10.1145/782814.782820
https://doi.org/10.1145/782814.782820
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