Zobrazeno 1 - 10
of 156
pro vyhledávání: '"Paul R. Gray"'
Publikováno v:
IEEE Journal of Solid-State Circuits. 41:2852-2859
A fully differential Doherty power amplifier (PA) is implemented in a 0.13-mum CMOS technology. The prototype achieves a maximum output power of +31.5 dBm with a peak power-added efficiency (PAE) of 36% (39% drain efficiency) with a GMSK modulated si
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ad866f97ea8c4cd3bf04406dd03d2454
https://doi.org/10.1109/jssc.2006.884832
https://doi.org/10.1109/jssc.2006.884832
Publikováno v:
IEEE Journal of Solid-State Circuits. 39:2139-2151
A 1.8-V 14-b 12-MS/s pseudo-differential pipeline analog-to-digital converter (ADC) using a passive capacitor error-averaging technique and a nested CMOS gain-boosting technique is described. The converter is optimized for low-voltage low-power appli
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e6a34f4f598be7323a208fd29c3a8d6b
https://doi.org/10.1109/jssc.2004.836232
https://doi.org/10.1109/jssc.2004.836232
Publikováno v:
IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications. 51:38-46
We present an adaptive digital technique to calibrate pipelined analog-to-digital converters (ADCs). Rather than achieving linearity by adjustment of analog component values, the new approach infers component errors from conversion results and applie
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fba1a880ab2f512a1cea47d4530f9dad
https://doi.org/10.1109/tcsi.2003.821306
https://doi.org/10.1109/tcsi.2003.821306
Autor:
Paul R. Gray, King-Chun Tsai
Publikováno v:
IEEE Journal of Solid-State Circuits. 34:962-970
This paper presents a 1-W, class-E power amplifier that is implemented in a 0.35-/spl mu/m CMOS technology and suitable for operations up to 2 GHz. The concept of mode locking is used in the design, in which the amplifier acts as an oscillator whose
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f1acd4c07abc6f90d58f6032b6ca195a
https://doi.org/10.1109/4.772411
https://doi.org/10.1109/4.772411
Autor:
Paul R. Gray, A.M. Abo
Publikováno v:
IEEE Journal of Solid-State Circuits. 34:599-606
A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6 /spl mu/m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without low-threshold de
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2bb0ae6118ce7af7e27d634a1188ab2d
https://doi.org/10.1109/4.760369
https://doi.org/10.1109/4.760369
Autor:
K.K. Onodera, Paul R. Gray
Publikováno v:
IEEE Journal of Solid-State Circuits. 33:753-761
A DS-CDMA demodulator uses analog sampled-data signal processing to achieve a 75-mW power dissipation and a 128-MS/s processing rate in a 1.2-/spl mu/m double-metal double-poly CMOS process. To demodulate the signal, a low-power passive correlation t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c31ed5eea50ce44d4010796f20497bd8
https://doi.org/10.1109/4.668990
https://doi.org/10.1109/4.668990
Publikováno v:
IEEE Journal of Solid-State Circuits. 33:1462-1469
A 13-bit, 1.4-MS/s, sixth-order cascaded sigma-delta modulator oversampling at 16 X is implemented in a 0.72 /spl mu/m complementary metal-oxide-semiconductor process for use in the baseband path of a radio-frequency receiver. The modulator achieves
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f6dd36f63398df9ab56642f437fcaee3
https://doi.org/10.1109/4.720392
https://doi.org/10.1109/4.720392
Autor:
Paul R. Gray, D.W. Cline
Publikováno v:
IEEE Journal of Solid-State Circuits. 31:294-303
A 13-b 5-MHz pipelined analog-to-digital converter (ADC) was designed with the goal of minimizing power dissipation. Power was reduced by using a high swing residue amplifier and by optimizing the per stage resolution. The prototype device fabricated
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::83242caf06ae0cd2ec2f53911b81da26
https://doi.org/10.1109/4.494191
https://doi.org/10.1109/4.494191
Publikováno v:
IEEE Journal of Solid-State Circuits. 31:448-451
A module generator (DSYN) creates optimized digital/analog converter (DAC) layouts given a set of specifications including performance constraints, a description of the implementation technology, and a set of design parameters. The generation process
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::28733726a2de8fe57a584bd4b00e359f
https://doi.org/10.1109/4.494207
https://doi.org/10.1109/4.494207
Autor:
Paul R. Gray, Thomas Byunghak Cho
Publikováno v:
IEEE Journal of Solid-State Circuits. 30:166-172
This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 /spl mu/m CMOS technology which achieves a power dissipation of 35 mW at full speed operation. Circuit techniques used to achieve this level of power dissipation incl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::58ff888068d3f3bd588cc74407f69ad8
https://doi.org/10.1109/4.364429
https://doi.org/10.1109/4.364429