Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Paul E. Landman"'
Autor:
Jesse Coulon, David Smith, Paul E. Landman, Mark Weaver, Manar El-Chammas, Jake Hu, Xiaopeng Li, Shigenobu Kimura
Publikováno v:
ISSCC
Wireless infrastructure imposes increasingly stringent requirements on data converters. To enable base stations with multi-carrier functionality, ADCs in the receive path need high sample rates with superior SFDR across 100s of MHz and several decade
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ad175d2679723d170fb31e5181169544
https://doi.org/10.1109/isscc.2015.7063038
https://doi.org/10.1109/isscc.2015.7063038
Autor:
V. Gupta, Yiqun Xie, L. Dyson, R. Gu, Paul E. Landman, Bhavesh G. Bhakta, John Powers, W. Mohammed, Ah-Lyan Yee, K. Heragu, Wai Lee, Lin Wu, Mustafa Ulvi Erdogan, B. Parthasarathy, Keith Brouse, Robert Floyd Payne, Song Wu, Srinath Ramaswamy
Publikováno v:
IEEE Journal of Solid-State Circuits. 40:2646-2657
A transceiver capable of 6.25-Gb/s data transmission across legacy communications equipment backplanes is described. To achieve a bit error rate (BER)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2447560f09f9be5f8da0f41cb5ece132
https://doi.org/10.1109/jssc.2005.856583
https://doi.org/10.1109/jssc.2005.856583
Autor:
Jan M. Rabaey, Paul E. Landman
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 15:571-587
Prompted by demands for portability and low-cost packaging, the electronics industry has begun to view power consumption as a critical design criterion. As such there is a growing need for tools that can accurately predict power consumption early in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0ba7fc54dcc9f35c63e5cdce73a2d0e6
https://doi.org/10.1109/43.503928
https://doi.org/10.1109/43.503928
Publikováno v:
IEEE Design & Test of Computers. 13:72-82
This CAD environment supports a high-level approach to power reduction, emphasizing optimizations at the algorithm and architecture levels of abstraction. An integrated set of analysis and optimization tools spans the design hierarchy, allowing the d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::faa741148a3526173fa0193658a3ac17
https://doi.org/10.1109/54.500202
https://doi.org/10.1109/54.500202
Autor:
Paul E. Landman, Jan M. Rabaey
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 3:173-187
This paper describes a novel strategy for generating accurate black-box models of datapath power consumption at the architecture level. This is achieved by recognizing that power consumption in digital circuits is affected by activity, as well as phy
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3785b01c83e2ca39c67684acf6e7c664
https://doi.org/10.1109/92.386219
https://doi.org/10.1109/92.386219
Autor:
Robert Floyd Payne, Bhavesh G. Bhakta, Ulvi Erdogan, Ah-Lyan Yee, Srinath Ramaswamy, L. Dyson, John Powers, B. Parthasarathy, Yiqun Xie, Lin Wu, Song Wu, R. Gu, Keith Brouse, W. Mohammed, Paul E. Landman, K. Heragu, Wai Lee, V. Gupta
Publikováno v:
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
A transmit architecture with a programmable 4-tap feedforward equalizer for 6.25 to 12.5 Gb/s serial communications through lossy channels is described. A 16:8-channel MUX/DEMUX chip fabricated in a 0.13 /spl mu/m 7M CMOS process demonstrates a near-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::15a38b7aef36a2961232cbd0ce92f5fd
https://doi.org/10.1109/isscc.2005.1493871
https://doi.org/10.1109/isscc.2005.1493871
Autor:
Keith Brouse, W. Mohammed, Bhavesh G. Bhakta, Ah-Lyan Yee, Song Wu, V. Gupta, B. Parthasarathy, Yiqun Xie, Srinath Ramaswamy, Paul E. Landman, Ulvi Erdogan, L. Dyson, Wai Lee, R. Gu, K. Heragu, John Powers, Robert Floyd Payne, Lin Wu
Publikováno v:
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
A 6.25 Gb/s serial receiver with a 4-tap adaptive DFE is implemented in a 0.13 /spl mu/m 7LM CMOS process. Direct cancellation of the first post-cursor ISI is achieved, enabling recovery of a data eye fully closed from channel losses and crosstalk. A
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cb067ab133c08f8eb2cfbd2c055e3314
https://doi.org/10.1109/isscc.2005.1493872
https://doi.org/10.1109/isscc.2005.1493872
Autor:
P. Fremrot, L. Dyson, Wai Lee, Ah-Lyan Yee, M. Frannhagen, V. Gupta, Paul E. Landman, K. Lewis, P. Bosshart, S. Johansson, R. Gu, J. Reynolds, Srinath Ramaswamy, B. Parthasarathy
Publikováno v:
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
A backplane interconnect ASIC with 62 Gb/s full-duplex aggregate throughput uses 3.1 Gb/s serial link technology organized as 20 bidirectional channels to realize bandwidth. The chip operates with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6b0377b013af3a52e98238fe07fb7db2
https://doi.org/10.1109/isscc.2002.992944
https://doi.org/10.1109/isscc.2002.992944
Autor:
L. Dyson, Wai Lee, V. Gupta, Song Wu, Ah-Lyan Yee, Srinath Ramaswamy, R. Gu, B. Parthasarathy, Paul E. Landman
Publikováno v:
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).
This paper describes I/O circuits that can be used in high-speed transceivers to communicate with next generation and legacy devices. We describe the transmitter and receiver front-end circuits that are designed to operate with dual termination volta
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::21bf136485164e18556b4a91aaab2162
https://doi.org/10.1109/vlsic.2002.1015049
https://doi.org/10.1109/vlsic.2002.1015049
Autor:
Paul E. Landman, Jan M. Rabaey
Publikováno v:
1993 European Conference on Design Automation with the European Event in ASIC Design.
Techniques for rapidly and accurately estimating power consumption based on high level descriptions of system architectures are described. This approach, based on stochastic modeling of bus statistics, achieves the accuracy traditionally associated w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::57406ab790ed86dbfe6281da5f198477
https://doi.org/10.1109/edac.1993.386449
https://doi.org/10.1109/edac.1993.386449