Zobrazeno 1 - 10
of 33
pro vyhledávání: '"Paul A. Packan"'
Autor:
D. Becher, P. Newman, A. Kornfeld, N. Arkali Radhakrishna, Sanjay Natarajan, S. Mudanai, K. Maurice, Paul A. Packan, Martin D. Giles, Titash Rakshit
Publikováno v:
2015 Symposium on VLSI Technology (VLSI Technology).
Random variation of threshold voltage (Vt) in MOSFETs plays a central role in determining the minimum operating voltage of products in a given process technology. Properly characterizing Vt variation requires a large volume of measurements of minimum
Autor:
M. Chahal, S. Novak, Paul A. Packan, C. Parker, S. Ramey, M. Agostinelli, Sanjay Natarajan, Mark Y. Liu, D. Becher, P. Nayak
Publikováno v:
IRPS
This paper details the transistor aging and gate oxide reliability of Intel's 14nm process technology. This technology introduces Intel's 2nd generation tri-gate transistor and the 4th generation of high-κ dielectrics and metal-gate electrodes. The
Publikováno v:
IEEE Transactions on Electron Devices. 53:2091-2097
In this paper, a detailed physical analysis and an analytical derivation of the degradation of the output resistance (Rout) observed in relatively long-channel laterally nonuniformly doped devices with halo implants are presented. Two-dimensional dev
Autor:
K. Fischer, Pulkit Jain, Sell Bernhard, P. Plekhanov, Swaminathan Sivakumar, S. Rajamani, R. James, Mark Y. Liu, C. Kenyon, L. Neiberg, Pete Smith, J. Wiedemer, M. Haran, M. Prince, Kevin Zhang, A. Bowonder, S. Morarka, R. Mehandru, B. Song, M. Agostinelli, Q. Fu, Y. Luo, W. Han, M. Heckscher, R. Grover, R. Patel, V. Chikarmane, S. Akbar, S. Chouksey, P. Patel, D. Hanken, I. Jin, L. Pipes, C. Parker, J. Sandford, M. Giles, Paul A. Packan, Tahir Ghani, A. Paliwal, E. Haralson, M. Bost, K. Tone, Sanjay Natarajan, M. Yang, Eric Karl, Hei Kam, R. Jhaveri, R. Heussner, T. Troeger, A. Dasgupta, S. Govindaraju, C. Pelto
Publikováno v:
2014 IEEE International Electron Devices Meeting.
A 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described. The
Autor:
Paul A. Packan, S. Mudanai, C. Auth, Chetan Prasad, S. Ramey, Martin D. Giles, Kaizad Mistry, Sanjay Natarajan, Ian R. Post, J. Hicks, S. Gupta, Srinivas Bodapati, K. Kuhn, M. Agostinelli
Publikováno v:
2014 IEEE International Reliability Physics Symposium.
A summary of NBTI variation is reported on large data-sets across five generations of Intel technologies (90 nm to 22 nm) and a comparison of statistical frameworks is utilized to show the universality of variation metrics across generations. Large v
Autor:
Paul A. Packan
Publikováno v:
MRS Bulletin. 25:18-21
The dominant device used in the semiconductor industry today is the silicon-based metal oxide semiconductor (MOS) transistor. The MOS transistor consists of a source, drain, channel, and gate region fabricated in single-crystal silicon (Figure 1). Th
Autor:
Ian R. Post, Kaizad Mistry, P. Vandervoorn, Chetan Prasad, A. Schmitz, Paul A. Packan, Dhruv Singh, B. Niu, M. Agostinelli, Daniel Pantuso, P. Bai, S. Ramey, Sanjay Natarajan, Travis Eiles, J. Thomas, Sell Bernhard, J. Hicks, Lei Jiang, C. Auth, Chia-Hong Jan, S. Suthram, Curtis Tsai
Publikováno v:
2013 IEEE International Reliability Physics Symposium (IRPS).
This paper describes various measurements on self-heat performed on Intel's 22nm process technology, and outlines its reliability implications. Comparisons to thermal modeling results and analytical data show excellent matching.
Autor:
Tahir Ghani, Richard Purser, Jingyoo Choi, Mark Y. Liu, Chris Parker, Ashwin Ashok, Jun He, Sangwoo Pae, Karen Lemay, Paul A. Packan, Bruce Woolery, Ryan Lu, Anthony St. Amour, Seok-Hee Lee
Publikováno v:
2010 IEEE International Reliability Physics Symposium.
High-K (HK) and Metal-Gate (MG) transistor reliability is very challenging both from the standpoint of introduction of new materials and requirement of higher field of operation for higher performance. In this paper, key and unique HK+MG intrinsic tr
Autor:
J. Seiple, L. Neiberg, R. Heussner, W. Han, S. Lodha, Abhishek Sharma, T. Troeger, Paul A. Packan, Oleg Golonzka, Swaminathan Sivakumar, B. Mattis, Mark Armstrong, Daniel B. Bergstrom, Tahir Ghani, Kevin Zhang, K. Dev, Anand Portland Murthy, J. Neirynck, Jun He, C. Kenyon, Cory E. Weber, G. Ding, L. Pipes, H. Deshpande, S. Pae, Y. Luo, J. Jopling, A. St. Amour, Robert James, Mark Y. Liu, J. Sebastian, Sanjay Natarajan, B. Song, Sell Bernhard, S. Akbar, Mark R. Brazier, C. Parker, S-H. Lee, K. Tone
Publikováno v:
2009 IEEE International Electron Devices Meeting (IEDM).
A 32nm logic technology for high performance microprocessors is described. 2nd generation high-k + metal gate transistors provide record drive currents at the tightest gate pitch reported for any 32nm or 28nm logic technology. NMOS drive currents are
Autor:
Paul A. Packan
Publikováno v:
Science. 285:2079-2081
For the past 30 years, transistor performance and density have doubled every 3 years, but now fundamental thermodynamic limits are being reached in critical areas, and unless new, innovative solutions are found, the current rate of improvement cannot