Zobrazeno 1 - 10
of 33
pro vyhledávání: '"Patrick, Justison"'
Autor:
Zhuo-Jie (George) Wu, Ping-Chuan Wang, Seungman Choi, Patrick Justison, Martin Gall, Jae-Kyu Cho, Takako Hirokawa, Yusheng Bian, Thomas Houghton, Vaishnavi Karra, Dan Moy, Karen Nummy, Dave Riggs, Norman Robson, Ian Melville, Ken Giewont
Publikováno v:
2023 Optical Fiber Communications Conference and Exhibition (OFC).
We report a study on moisture effect on optical performance of monolithic silicon photonics technologies featuring V-grooves for self-aligned fiber attach. Chip-level hermetic sealing was achieved by implementing moisture barrier for the fiber couple
Publikováno v:
IEEE Electron Device Letters. 41:288-291
Front and back ends of line (FEOL and BEOL) self-heating and mutual heating are important barriers to a sustained increase in processor speed and density. In this context, the severity of transient Joule heating in scaled interconnects under a variet
Autor:
Haojun Zhang, Patrick Justison, Robert Fox, Scott Pozder, Dewei Xu, Seung-Yeop Kook, Zhiguo Sun, Rod Augur
Publikováno v:
International Symposium on Microelectronics. 2019:000591-000594
Lower RC delay is vital to achieve optimal and competitive circuit performance and hence drives the endlessly pursued BEOL integration scheme advancement. To date low-k dielectric materials, i.e., fluorine-doped oxides, carbon-doped oxide (SiCOH), to
Autor:
John C. Malinowski, Zhuo-Jie Wu, Kristina Young-Fisher, Patrick Justison, Jean Trewhella, Haojun Zhang, Millete Carino
Publikováno v:
2020 IEEE 70th Electronic Components and Technology Conference (ECTC).
The acceptance of Wafer Level Chip Scale Package (WLCSP) technology is significantly increasing for use in small devices such as mobile phones, wearable, RF antenna packages, and health monitor sensors. WLCSP structures can have a few thin redistribu
Autor:
SangHoon Shin, Muhammad A. Alam, Haojun Zhang, Cathryn Christiansen, Patrick Justison, Woojin Ahn, Tian Shen
Publikováno v:
IEEE Transactions on Electron Devices. 64:3555-3562
Spatially resolved precise prediction of local temperature ${T}(\textit {x,y,z})$ is essential to evaluate Arrhenius-activated interconnect (e.g., electromigration) and transistor reliability (e.g., NBTI, HCI, and TDDB). A 3-D finite-element modeling
Publikováno v:
IEEE Electron Device Letters. 38:119-122
Low- $\kappa $ SiCOH reliability is a growing concern for integrated circuit reliability. An important consideration for product qualification involves the accurate extrapolation to the low percentile failures based on the results from a group of sam
Publikováno v:
IRPS
Stacking of chips vertically will reduce the interconnection resistance and as a result enhance data communication between chips. Memory chip to logic chip integration requires close proximity to improve the performance and is an alternate to SOC typ
Publikováno v:
IRPS
The MOL PC-CA TDDB reliability is systematically evaluated for the 1.98V IO devices with Self-Aligned Contact (SAC) and top off oxide process. Compared to the thin oxide devices, significant reliability improvement from both t63 and β can be achieve
Publikováno v:
IEEE Transactions on Electron Devices. 63:755-759
This paper proposes a methodology to determine a realistic time-dependent dielectric breakdown failure rate. The in-die constant voltage stress was performed to determine the chip level Weibull shape ( $\beta _{\mathrm{die}})$ and voltage acceleratio
Autor:
Thomas A. Wassick, John P. Cincotta, Oswaldo Chacon, Theo Anemikos, Hugues Gagnon, Robert Martel, Charles Carey, Samantha Donavan, Zhuo-Jie Wu, Patrick Justison, Doug Hunt
Publikováno v:
2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
To enable higher computing power in a single chip, there is demand for increasing die size for high performance applications in advanced nodes. Due to the weak mechanical properties of the low-k and ultra low-k (ULK) dielectrics in advanced technolog