Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Patricia M. Sagmeister"'
Autor:
Jan van Lunteren, Patricia M. Sagmeister, Gero Dittmann, Andreas Herkersdorf, Andreas Döring, Maria Gabrani
Publikováno v:
Computer Networks. 41:623-640
We present a design methodology for a modular network processor architecture that leads to a balanced, servicedefined mix between programmable processor cores, configurable hardware assists, and specialized coprocessors. Whereas the processor cores a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3f37312e3667bc7d7109b6df0875011c
https://doi.org/10.1016/s1389-1286(02)00453-x
https://doi.org/10.1016/s1389-1286(02)00453-x
Autor:
Simon Künzli, Lothar Thiele, Patricia M. Sagmeister, Samarjit Chakraborty, Andreas Herkersdorf
Publikováno v:
Computer Networks. 41:641-665
The designs of most systems-on-a-chip (SoC) architectures rely on simulation as a means for performance estimation. Such designs usually start with a parameterizable template architecture, and the design space exploration is restricted to identifying
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8e7076e6508c4a7204d94f11485e5cdc
https://doi.org/10.1016/s1389-1286(02)00454-1
https://doi.org/10.1016/s1389-1286(02)00454-1
Autor:
Daniel Brand, Youngsoo Shin, Reinaldo A. Bergamaschi, John A. Darringer, J. K. Morrell, Subhrajit Bhattacharya, Andreas Herkersdorf, Patricia M. Sagmeister, Indira Nair
Publikováno v:
IBM Journal of Research and Development. 46:691-707
The paper describes the need for early analysis tools to enable developers of today's system-on-a-chip (SoC) designs to take advantage of pre-designed components, such as those found in the IBM Blue Logic® Library, and rapidly explore high-level d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::39b3b3274049446cb096c77afc492703
https://doi.org/10.1147/rd.466.0691
https://doi.org/10.1147/rd.466.0691
Publikováno v:
ANCS
Network processors use highly parallel architectures to improve performance and reach multi-gigabit line-speeds. In this paper, we emulate a pipeline in a highly parallel non-programmable industrial InfiniBand Host Channel Adapter to make a performan
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::11520a19dd85910cd1258a52cc1d939f
https://doi.org/10.1145/1477942.1477972
https://doi.org/10.1145/1477942.1477972
Autor:
William J. Starke, Guy Lynn Guthrie, Patricia M. Sagmeister, Charles F. Marino, Florian A. Auernhammer, M. S. Siegel, John Steven Dodson, David M. Daly, Bart Blaner, Jeffrey A. Stuecheli
Publikováno v:
IBM Journal of Research and Development. 59:3:1-3:13
In this paper, we describe the IBM POWER8™ cache, interconnect, memory, and input/output subsystems, collectively referred to as the “nest.” This paper focuses on the enhancements made to the nest to achieve balanced and scalable designs, rangi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fe2d630e0d0814c510f8b629a40af02a
https://doi.org/10.1147/jrd.2014.2376131
https://doi.org/10.1147/jrd.2014.2376131