Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Pasquale Cocchini"'
Publikováno v:
Proceedings of the 28th Asia and South Pacific Design Automation Conference.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::be38ad7180f608f03bb960be33831ce0
https://doi.org/10.1145/3566097.3567843
https://doi.org/10.1145/3566097.3567843
Autor:
Debjit Pal, Yi-Hsiang Lai, Shaojie Xiang, Niansong Zhang, Hongzheng Chen, Jeremy Casas, Pasquale Cocchini, Zhenkun Yang, Jin Yang, Louis-Noël Pouchet, Zhiru Zhang
Publikováno v:
Proceedings of the 59th ACM/IEEE Design Automation Conference.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::06e5f6a4631fef6349b3b038e3d6d41b
https://doi.org/10.1145/3489517.3530681
https://doi.org/10.1145/3489517.3530681
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 23:451-463
We study scaling in the context of typical block-level wiring distributions, and identify its impact on the design process. In particular, we study the implications of exponentially increasing repeater and clocked repeater counts on the algorithms an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::217c23740e009c7e442ccc53509dd046
https://doi.org/10.1109/tcad.2004.825841
https://doi.org/10.1109/tcad.2004.825841
Publikováno v:
ISPD
We present the results of scaling studies in the context of typical block-level wiring distributions, and study the impact of the identified trends on the post-RTL design process. In particular, we look at the implications of exponentially increasing
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e7af7c98353ec144da47462cc03311e2
https://doi.org/10.1145/640000.640014
https://doi.org/10.1145/640000.640014
Autor:
Pasquale Cocchini
Publikováno v:
ICCAD
For many years, CMOS process scaling has allowed a steady increase in the operating frequency and integration density of integrated circuits. Only recently, however, have we reached a point where it takes several clock cycles for global signals to tr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a85d9cc757caddf0b366607e3dfcdbc4
https://doi.org/10.1145/774572.774612
https://doi.org/10.1145/774572.774612