68-channel neural signal processing system-on-chip with integrated feature extraction, compression, and hardware accelerators for neuroprosthetics in 22 nm FDSOI.

Autor: Guo L; Faculty of Electrical and Computer Engineering, School of Engineering Sciences, Dresden University of Technology, Dresden, Germany., Weiße A; Faculty of Electrical and Computer Engineering, School of Engineering Sciences, Dresden University of Technology, Dresden, Germany., Zeinolabedin SMA; Department of Electrical and Computer Engineering, College of Engineering, University of Utah, Salt Lake City, UT, United States., Schüffny FM; Faculty of Electrical and Computer Engineering, School of Engineering Sciences, Dresden University of Technology, Dresden, Germany., Stolba M; Faculty of Electrical and Computer Engineering, School of Engineering Sciences, Dresden University of Technology, Dresden, Germany., Ma Q; Faculty of Electrical and Computer Engineering, School of Engineering Sciences, Dresden University of Technology, Dresden, Germany., Wang Z; Faculty of Electrical and Computer Engineering, School of Engineering Sciences, Dresden University of Technology, Dresden, Germany., Scholze S; Faculty of Electrical and Computer Engineering, School of Engineering Sciences, Dresden University of Technology, Dresden, Germany., Dixius A; Faculty of Electrical and Computer Engineering, School of Engineering Sciences, Dresden University of Technology, Dresden, Germany., Berthel M; Faculty of Electrical and Computer Engineering, School of Engineering Sciences, Dresden University of Technology, Dresden, Germany., Partzsch J; Faculty of Electrical and Computer Engineering, School of Engineering Sciences, Dresden University of Technology, Dresden, Germany., Walter D; Faculty of Electrical and Computer Engineering, School of Engineering Sciences, Dresden University of Technology, Dresden, Germany., Ellguth G; Faculty of Electrical and Computer Engineering, School of Engineering Sciences, Dresden University of Technology, Dresden, Germany., Höppner S; Faculty of Electrical and Computer Engineering, School of Engineering Sciences, Dresden University of Technology, Dresden, Germany., George R; Faculty of Electrical and Computer Engineering, School of Engineering Sciences, Dresden University of Technology, Dresden, Germany., Mayr C; Faculty of Electrical and Computer Engineering, School of Engineering Sciences, Dresden University of Technology, Dresden, Germany.

Publikováno v: Frontiers in neuroscience [Front Neurosci] 2024 Oct 23; Vol. 18, pp. 1432750. Date of Electronic Publication: 2024 Oct 23 (Print Publication: 2024).

VLSI implementation of a conductance-based multi-synapse using switched- capacitor circuits

Autor: Noack, M, Krause, M, Mayr, C, Partzsch, J, Schüffny, R

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=od_______885::f57b76918d66edf96f120ebab92980ac
https://doi.org/10.5167/uzh-107838

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Efficient Reward-Based Structural Plasticity on a SpiNNaker 2 Prototype.

Autor: Yan Y, Kappel D, Neumarker F, Partzsch J, Vogginger B, Hoppner S, Furber S, Maass W, Legenstein R, Mayr C

Publikováno v: IEEE transactions on biomedical circuits and systems [IEEE Trans Biomed Circuits Syst] 2019 Jun; Vol. 13 (3), pp. 579-591. Date of Electronic Publication: 2019 Mar 27.

Memory-Efficient Deep Learning on a SpiNNaker 2 Prototype.

Autor: Liu C; Chair of Highly-Parallel VLSI-Systems and Neuromorphic Circuits, Department of Electrical Engineering and Information Technology, Institute of Circuits and Systems, Technische Universität Dresden, Dresden, Germany., Bellec G; Institute for Theoretical Computer Science, Graz University of Technology, Graz, Austria., Vogginger B; Chair of Highly-Parallel VLSI-Systems and Neuromorphic Circuits, Department of Electrical Engineering and Information Technology, Institute of Circuits and Systems, Technische Universität Dresden, Dresden, Germany., Kappel D; Chair of Highly-Parallel VLSI-Systems and Neuromorphic Circuits, Department of Electrical Engineering and Information Technology, Institute of Circuits and Systems, Technische Universität Dresden, Dresden, Germany.; Institute for Theoretical Computer Science, Graz University of Technology, Graz, Austria.; Bernstein Center for Computational Neuroscience, III Physikalisches Institut - Biophysik, Georg-August Universität, Göttingen, Germany., Partzsch J; Chair of Highly-Parallel VLSI-Systems and Neuromorphic Circuits, Department of Electrical Engineering and Information Technology, Institute of Circuits and Systems, Technische Universität Dresden, Dresden, Germany., Neumärker F; Chair of Highly-Parallel VLSI-Systems and Neuromorphic Circuits, Department of Electrical Engineering and Information Technology, Institute of Circuits and Systems, Technische Universität Dresden, Dresden, Germany., Höppner S; Chair of Highly-Parallel VLSI-Systems and Neuromorphic Circuits, Department of Electrical Engineering and Information Technology, Institute of Circuits and Systems, Technische Universität Dresden, Dresden, Germany., Maass W; Institute for Theoretical Computer Science, Graz University of Technology, Graz, Austria., Furber SB; Advanced Processor Technologies Group, School of Computer Science, University of Manchester, Manchester, United Kingdom., Legenstein R; Institute for Theoretical Computer Science, Graz University of Technology, Graz, Austria., Mayr CG; Chair of Highly-Parallel VLSI-Systems and Neuromorphic Circuits, Department of Electrical Engineering and Information Technology, Institute of Circuits and Systems, Technische Universität Dresden, Dresden, Germany.

Publikováno v: Frontiers in neuroscience [Front Neurosci] 2018 Nov 16; Vol. 12, pp. 840. Date of Electronic Publication: 2018 Nov 16 (Print Publication: 2018).