Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Parthajit Bhattacharya"'
Autor:
Parthajit Bhattacharya, Girish Patankar, Hillol Maity, Indranil Sengupta, Santanu Chattopadhyay
Publikováno v:
2021 IEEE International Test Conference India (ITC India).
Next-generation devices are expected to have higher mobility, which forces the device packaging to be small. Small devices enforce stringent power requirements for the embedded VLSI circuits. In the test mode, these circuits dissipate more power comp
Autor:
Indranil Sengupta, Kaushik Khatua, Hillol Maity, Parthajit Bhattacharya, Girish Patankar, Santanu Chattopadhyay
Publikováno v:
ISDCS
During test mode, switching activity in scan-chain integrated circuits increase. As a result, the peak and average power dissipation in test mode often become higher than the normal mode. This can result in yield loss, heat damage to the circuit unde
Autor:
Kaushik Khatua, Parthajit Bhattacharya, Hillol Maity, Santanu Chattopadhyay, Indranil Sengupta, Girish Patankar
Publikováno v:
ICIT
Conventional pseudo-random testing in Built-InSelf-Test (BIST) usually requires a huge amount of testing time. This issue can be addressed with a Weighted Random Pattern generation that can produce test patterns in order to achieve high fault coverag
Autor:
Hillol Maity, Parthajit Bhattacharya, Girish Patankar, Kaushik Khatua, Santanu Chattopadhyay, Indranil Sengupta
Publikováno v:
TENCON
11This work is partially supported by the research project sponsored by the Synopsys Inc., USAWith the recent advancements of FPGA (Field Programmable Gate Array), circuits in AND-XOR plane gets its fair share of advantages due to the high testabilit
Publikováno v:
ITC
Diagnosis with a modern day low pin convolution compressor is difficult. Generally, it is done in two steps. In the first step, known as failure mapping, failures are mapped to the scan cells from the faulty responses recorded at compressor outputs o
Autor:
Rohit Kapur, Pramod Notiyath, Parthajit Bhattacharya, Ashok Anbalan, Jyotirmoy Saikia, Tammy Fernandes, Santosh Kulkarni, Rajesh Uppuluri
Publikováno v:
Asian Test Symposium
Scan compression technology is essentially IP that provides an interface between the scan-inputs/outputs and the internal scan chains. The IP configuration that is put into the design is based upon some user specified constraints that are related to