Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Paritosh Bhoraskar"'
Autor:
Matthew D. McShea, Huseyin Dinc, Ahmed Mohamed Abdelatty Ali, Joel Prabhakar, Mohit Kumar, Ryan Bunch, Scott Gregory Bardsley, Scott Puckett, Paritosh Bhoraskar, Christopher Daniel Dillon
Publikováno v:
ISSCC
High sample rate ADCs with high input bandwidth and low power consumption enable direct RF sampling, more integration, flexibility and lower cost for communication, instrumentation and other applications. The state of the art of interleaved RF conver
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7b8966e36621dd0e5a0ebadfddb4164b
https://doi.org/10.1109/isscc19947.2020.9063011
https://doi.org/10.1109/isscc19947.2020.9063011
Autor:
Ahmed M. A. Ali, Huseyin Dinc, Paritosh Bhoraskar, Chris Dillon, Scott Puckett, Bryce Gray, Carroll Speir, Jonathan Lanford, Janet Brunsilius, Peter R. Derounian, Brad Jeffries, Ushma Mehta, Matthew McShea, Russell Stop
Publikováno v:
IEEE Journal of Solid-State Circuits. 49:2857-2867
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4922538aa9e4917858a710a8db1824c0
https://doi.org/10.1109/jssc.2014.2361339
https://doi.org/10.1109/jssc.2014.2361339
Autor:
Ning Zhu, Huseyin Dinc, Scott Gregory Bardsley, Qicheng Yu, Jon Lanford, Gerry Taylor, Christopher Daniel Dillon, Scott Puckett, Paritosh Bhoraskar, Ushma Mehta, Andrew Stacy Morgan, Ryan Bunch, Matt McShea, Peter Derounian, Ahmed Mohamed Abdelatty Ali, Bryce Gray, Ralph Moore
Publikováno v:
VLSI Circuits
We describe a 14-bit 2.5GS/s non-interleaved pipelined ADC that relies on correlation-based background calibrations to correct the inter-stage gain, settling (dynamic), kick-back and memory errors. A new technique is employed to inject a large dither
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::267a44cdedf37b445c775db41d1b4213
https://doi.org/10.1109/vlsic.2016.7573537
https://doi.org/10.1109/vlsic.2016.7573537
Autor:
Jeff Bray, D Lattimore, R. Sneed, Scott Gregory Bardsley, G. Patterson, Andrew Stacy Morgan, R. Stop, M. Hensley, Ahmed Mohamed Abdelatty Ali, Scott Puckett, Christopher Daniel Dillon, Carroll C. Speir, Paritosh Bhoraskar, Huseyin Dinc
Publikováno v:
IEEE Journal of Solid-State Circuits. 45:2602-2612
This paper describes a 16-bit 250 MS/s ADC fabricated on a 0.18 BiCMOS process. The ADC has an integrated input buffer with a new linearization technique that improves its distortion by 5-10 dB and lowers its power consumption by 70% relative to the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7f98d99d6ca4db223e7958bca3af1022
https://doi.org/10.1109/jssc.2010.2073194
https://doi.org/10.1109/jssc.2010.2073194
Autor:
Ahmed Mohamed Abdelatty Ali, Paritosh Bhoraskar, Peter Derounian, Carroll C. Speir, Bryce Gray, Matt McShea, Scott Puckett, Brad P. Jeffries, Ho-Young Lee, Jonathan Lanford, Ushma Mehta, Christopher Daniel Dillon, David Jarman, Huseyin Dinc, Janet Brunsilius
Publikováno v:
ISSCC
We describe a 14-bit 1GS/s pipelined ADC that relies on correlation-based background calibration to correct the inter-stage gain, settling (dynamic) and memory errors. An effective dithering technique is embedded in the calibration signal to break th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::887106ee54aa8296aa360e8dc543f4e3
https://doi.org/10.1109/isscc.2014.6757522
https://doi.org/10.1109/isscc.2014.6757522
Autor:
Carroll C. Speir, Robert Sneed, Paritosh Bhoraskar, M. Hensley, David Lattimore, Scott Puckett, Christopher Daniel Dillon, Greg Patterson, Scott Gregory Bardsley, Andrew Stacy Morgan, Russell Stop, Jeff Bray, Ahmed Mohamed Abdelatty Ali
Publikováno v:
ISSCC
Wireless communication applications have driven the development of high-resolution A/D converters (ADCs) with high sample rates, good AC performance and IF sampling capability to enable wider cellular coverage, more carriers, and to simplify the syst
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::20c386fbc6818ccf416834f62e08746f
https://doi.org/10.1109/isscc.2010.5433923
https://doi.org/10.1109/isscc.2010.5433923
Autor:
Paritosh Bhoraskar, Yun Chiu
Publikováno v:
2007 IEEE Asian Solid-State Circuits Conference.
A 0.13-mum CMOS dual-loop digital DLL for multiphase clock generation and synchronization is presented. Ten clock phases are produced and locked to a first reference clock by the inner loop, while the outer loop further aligns all phases simultaneous
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4ff313c1064eca13b512ef83cb7d65b9
https://doi.org/10.1109/asscc.2007.4425736
https://doi.org/10.1109/asscc.2007.4425736