Zobrazeno 1 - 10
of 28
pro vyhledávání: '"Paresh Limaye"'
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 1:1885-1894
A novel low-temperature Cu-Cu bonding approach called the insertion bonding technique has been developed. This technique hinges on the introduction of a tangential pressure at the metal-metal interface, which leads to a high localized plastic deforma
Publikováno v:
ECS Transactions. 34:523-528
3D integration requires the realisation of electrical interconnects between multiple vertically stacked Si devices. Solder based, fine pitch, micro-bump connections are a promising approach for making die-to-die or die-to-wafer interconnections mainl
Autor:
Philippe Soussan, Riet Labie, Alain Phommahaxay, Rahul Agarwal, Gilbert Lecarpentier, W. Zhang, Paresh Limaye
Publikováno v:
Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT). 2010:001254-001281
25 um thick dies, mounted on thick carrier die, were placed on a 300mm landing wafer using the High Accuracy Die Bonder SET-FC300. The bonding process was either Cu/Cu or Cu/Sn with respective pitch of 10μm and 40μm. A special test structure was de
Autor:
Konstantina Lambrinou, Ingrid De Wolf, Paresh Limaye, Bert Verlinden, Wout Maurissen, Bart Vandevelde
Publikováno v:
Journal of Electronic Materials. 38:1881-1895
This work addresses a new mode of brittle failure that occurs in the bulk of tin-based lead-free solder joints, unlike the typical brittle failures that occur in the interfacial intermetallics. Brittle failures in the joint bulk result from the low-t
Publikováno v:
IEEE Transactions on Advanced Packaging. 31:51-57
Electroplated pure tin bumping as a lead-free alternative for ultra fine pitch applications is a relatively easy process and has provided us with comparable results to eutectic Sn/Pb for thermal cycling reliability. Experimentally, it has been report
Publikováno v:
Microelectronics Reliability. 47:215-222
The development of a simplified analytical model to describe the thermal history of a printed circuit board assembly (PCA) during convective reflow soldering is discussed in this paper. Verification of the assumptions was done by Finite Element Model
Publikováno v:
Scopus-Elsevier
This paper deals with a comparison study between SnPb and SnAgCu solder joint reliability. The comparison is based on non-linear finite element modelling. Three packages have been selected: silicon CSP, underfilled flip chip and QFN package. Also the
Autor:
Paresh Limaye, Vladimir Cherman, Bart Vandevelde, Nga P. Pham, Eric Beyne, Philippe Soussan, Nele Van Hoovels, Nina Tutunjyan, Deniz Sabuncuoglu Tezcan, Roelof Jansen, Harrie Tilmans
Publikováno v:
2011 IEEE 61st Electronic Components and Technology Conference (ECTC).
This paper presents a 0-level packaging technology for (RF-)MEMS implementing vertical feedthroughs or through-Si-via's (TSVs) and metal bonding. A thinned capping substrate (100μm thick) equipped with Cu-coated TSVs is bonded to a MEMS substrate. T
Autor:
Vladimir Cherman, Steven Thijs, Wouter Ruythooren, Dimitri Linten, Dimitrios Velenis, I. De Wolf, J. Van Olmen, Paresh Limaye, Riet Labie, M. de Potter de ten Broeck, Morin Dehan, V. Simons, Michal Rakowski, Wim Dehaene, Antonio Pullini, Herman Oprins, Igor Loi, Miro Cupac, D. Perry, G. Katti, Marc Nelis, G. Van der Plas, Youssef Travaly, Federico Angiolini, Abdelkarim Mercha, C. Torregiani, N. Minas, Alain Phommahaxay, A. Opdebeeck, Eric Beyne, Rahul Agarwal, Pol Marchal, Michele Stucchi, S Bronckers, B. De Wachter, Luca Benini, Bart Vandevelde
Publikováno v:
ISSCC
In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact of TSV on BEOL interconnect reliability is limited, no failures have been observed. The impact of TSV stress on MOS devices causes shi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d5977e2f158201f29c9dfb9475ff5464
http://hdl.handle.net/11585/106158
http://hdl.handle.net/11585/106158
Autor:
Vladimir Cherman, Paresh Limaye, Nga P. Pham, Harrie Tilmans, Deniz Sabuncuoglu Tezcan, Varela Pedreira Olalla, P. Czarnecki
Publikováno v:
2010 12th Electronics Packaging Technology Conference.
This paper presents a zero-level packaging technology for hermetic encapsulation of MEMS. The technology relies on the “chip capping” of the MEMS using a metallic bond made by means of diffusion soldering of a Cu-Sn system at a temperature of aro