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pro vyhledávání: '"Parag Biswas"'
Publikováno v:
Engineering Science and Technology, an International Journal. 23:1364-1373
A full-swing high-speed hybrid Full Adder (FA) cell based on Gate Diffusion Input (GDI) technique and Conventional Complementary Metal-Oxide Semiconductor (CCMOS) logic has been proposed in this work. The design has been verified and compared with te
Autor:
Md. Shihabul Alam, Mainul Hossain, Hasan U. Zaman, Sharnali Islam, Parag Biswas, Mehedi Hasan
Publikováno v:
ICCCNT
A new carry generation scheme for carry out bit of a 4-bit carry look-ahead (CLA) adder is presented. To analyze performance, proposed design for carry-out bit was implemented and verified in Cadence Virtuoso environment in 90nm technology. Performan
Autor:
Md. Jobayer Hossein, Uttam Kumar Saha, Muhammad Saddam Hossain, Parag Biswas, Md. Ashik Zafar Dipto, Mehedi Hasan
Publikováno v:
2019 International Conference on Computer Communication and Informatics (ICCCI).
Binary magnitude comparator is considered as an elementary apparatus in Arithmetic Logic Unit. Due to increased use of portable devices nowadays, energy efficient designs having less delay have become essential. This research introduces a new two-bit
Publikováno v:
2018 Fourth International Conference on Research in Computational Intelligence and Communication Networks (ICRCICN).
Smart Home Systems have achieved great interest in the recent years to make people’s life easier and more comfortable. Smart home system offers people to control home environment in efficient and comfortable manner. Technological advancement in rec