Zobrazeno 1 - 10
of 31
pro vyhledávání: '"Paolo Madoglio"'
Autor:
Yorgos Palaskas, Thomas Bauernfeind, Jorn Angel, Dimo Martev, Peter Preyler, Ashoke Ravi, Eshel Gordon, Ofir Degani, Timo Gossmann, Sven Hampel, Andreas Holm, Peter Plechinger, Rotem Banin, Thomas Mayer, Paolo Madoglio, Petra Schubert, Jakob Tomasik, Zdravko Boos
Publikováno v:
IEEE Journal of Solid-State Circuits. 55:1830-1841
A digital polar transmitter is presented that uses a digital-to-time-converter (DTC) for wide-channel phase modulation with multiband support. DTC-based phase modulation enables high-efficiency polar operation with high-efficiency RFDAC. The transmit
Autor:
Jakob Tomasik, Rotem Banin, Zdravko Boos, P. Schubert, Ashoke Ravi, T. Mayer, Ofir Degani, T. Bauernfeind, P. Plechinger, Sven Hampel, Peter Preyler, Yorgos Palaskas, Paolo Madoglio, Eshel Gordon, J. Angel
Publikováno v:
ESSCIRC
A digital polar transmitter is presented that uses a digital-to-time-converter (DTC) to enable high-efficiency polar RFDAC for multiband and wide-channel applications. The transmitter uses coarse division inherent in DTC operation to generate TX outp
Autor:
Kailash Chandarshekar, Yorgos Palaskas, David J. Allstot, Paolo Madoglio, Parmoon Seddighrad, Hongtao Xu
Publikováno v:
ISCAS
A digital switched-capacitor transformer-combining power amplifier (SCPA) that uses load modulation to achieve efficiency peaking at 0, −6, and −12 dB backoff levels is beneficial for signals with high peak-to-average power ratios (PAPR). The PA
Autor:
Khoa Minh Nguyen, Muhammad Faisal, Hyung Seok Kim, Satoshi Suzuki, Paolo Madoglio, Amr Fahim, Yorgos Palaskas, Zhichao Zhang, Hongtao Xu, Tan Yulin, Luis Cuellar, Stefano Pellerano, Jianyong Xie, Yanjie Wang, Kailash Chandrashekar, Parmoon Seddighrad, Ashoke Ravi, Divya Shree Vemparala, Thomas A. Tetzlaff, Brent Carlton, William Yee Li, Vaibhav Vaidya
Publikováno v:
ISSCC
To benefit from Moore's law and minimize form-factor and active power consumption, digital-rich SoCs should be integrated in the most advanced technology node. If the transceiver is integrated in a different technology node, multi-chip solutions are
Autor:
Ashoke Ravi, Carlos Ornelas, D. Shi, Hyung Seok Kim, William Yee Li, Kailash Chandrashekar, Pin-en Su, Paolo Madoglio
Publikováno v:
IEEE Journal of Solid-State Circuits. 48:1721-1729
A 6-bit time-to-digital converter that achieves mismatch free operation by using a single delay cell and sampling flip-flop is presented. The proposed TDC was integrated in a digital fractional-N PLL fabricated in a 32-nm digital SoC CMOS process for
Autor:
Ashoke Ravi, Yorgos Palaskas, J. E. Zarate-Roldan, Paolo Madoglio, Kailash Chandrashekar, Hasnain Lakdawala, Stefano Pellerano, Masoud Sajadieh, O. Bochobza-Degani, Hongtao Xu, Luis Cuellar, Marian Verhelst, M. Aguirre-Hernandez
Publikováno v:
IEEE Journal of Solid-State Circuits. 47:3184-3196
A digital outphasing transmitter is presented for 2.4-GHz WiFi. The transmitter consists of two delay-based phase modulators and a 26-dBm integrated switching class-D power amplifier. The delay-based phase modulator delays incoming LO edges with a re
Autor:
Salvatore Levantino, Carlo Samori, Davide Tasca, Paolo Madoglio, Marco Zanuso, Andrea L. Lacaita
Publikováno v:
EURASIP Journal on Embedded Systems, Vol 2010, Iss 1, p 175764 (2010)
EURASIP Journal on Embedded Systems, Vol 2010 (2010)
EURASIP Journal on Embedded Systems, Vol 2010 (2010)
This paper describes the design of an All-Digital Phase Locked Loop (AD-PLL) for wireless applications in the WiMAX 3.3–3.8 GHz bandwidth. The time/digital converter (TDC) sets the in-band noise and it may be responsible for the presence of spuriou
Publikováno v:
IEEE Journal of Solid-State Circuits. 44:3422-3433
This paper presents a fractional frequency divider-by-1.25 and associated all-digital calibration circuitry. The divider can be used in a wireless transceiver to prevent direct or harmonic pulling of the VCO by the power amplifier. Timing errors betw
Publikováno v:
PP (2009): 1.
info:cnr-pdr/source/autori:Marco Zanuso, Paolo Madoglio, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita/titolo:Time-to-Digital Converter for Frequency Synthesis based on a Digital Bang-Bang DLL/doi:/rivista:/anno:2009/pagina_da:1/pagina_a:/intervallo_pagine:1/volume:PP
info:cnr-pdr/source/autori:Marco Zanuso, Paolo Madoglio, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita/titolo:Time-to-Digital Converter for Frequency Synthesis based on a Digital Bang-Bang DLL/doi:/rivista:/anno:2009/pagina_da:1/pagina_a:/intervallo_pagine:1/volume:PP
This paper presents the design of a time-to-digital converter (TDC) suitable for a 3.5-GHz all-digital phase-lock loop (PLL). The converter is based on a digital bang-bang delay-lock loop, which allows constant resolution over process and temperature
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::bc86798e091f4aec5b726637b75dde21
http://hdl.handle.net/11311/560588
http://hdl.handle.net/11311/560588
Autor:
Salvatore Levantino, Marco Zanuso, Paolo Madoglio, Davide Tasca, Carlo Samori, Andrea L. Lacaita
Publikováno v:
(2009).
info:cnr-pdr/source/autori:Salvatore Levantino, Marco Zanuso, Paolo Madoglio, Davide Tasca, Carlo Samori, Andrea L. Lacaita/titolo:AD-PLL for WiMAX with Digital Bang-Bang TDC and Glitch Correction Logic/doi:/rivista:/anno:2009/pagina_da:/pagina_a:/intervallo_pagine:/volume
info:cnr-pdr/source/autori:Salvatore Levantino, Marco Zanuso, Paolo Madoglio, Davide Tasca, Carlo Samori, Andrea L. Lacaita/titolo:AD-PLL for WiMAX with Digital Bang-Bang TDC and Glitch Correction Logic/doi:/rivista:/anno:2009/pagina_da:/pagina_a:/intervallo_pagine:/volume
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=cnr_________::afc202008d04ea5334135c09f2d4474a
https://publications.cnr.it/doc/25396
https://publications.cnr.it/doc/25396