Zobrazeno 1 - 10
of 120
pro vyhledávání: '"Pandya, Paritosh"'
Metric Temporal Logic (MTL) and Timed Propositional Temporal Logic (TPTL) extend Linear Temporal Logic (LTL) for real-time constraints, with MTL using time-bounded modalities and TPTL employing freeze quantifiers. Satisfiability for both is generally
Externí odkaz:
http://arxiv.org/abs/2411.00117
We investigate the decidability of the ${0,\infty}$ fragment of Timed Propositional Temporal Logic (TPTL). We show that the satisfiability checking of TPTL$^{0,\infty}$ is PSPACE-complete. Moreover, even its 1-variable fragment (1-TPTL$^{0,\infty}$)
Externí odkaz:
http://arxiv.org/abs/2309.00386
In this paper, we study the extension of 1-clock Alternating Timed Automata (1-ATA) with the ability to read in both forward and backward direction, the 2-Way 1-clock Alternating Timed Automata (2-Way 1-ATA). We show that subclass of 2-Way 1-ATA with
Externí odkaz:
http://arxiv.org/abs/2107.12986
Metric Temporal Logic (MTL) and Timed Propositional Temporal Logic (TPTL) are prominent real-time extensions of Linear Temporal Logic (LTL). In general, the satisfiability checking problem for these extensions is undecidable when both the future U an
Externí odkaz:
http://arxiv.org/abs/2105.09534
Autor:
Pandya, Paritosh K., Wakankar, Amol
Publikováno v:
EPTCS 305, 2019, pp. 91-106
A system with sporadic errors (SSE) is a controller which produces high quality output but it may occasionally violate a critical requirement REQ(I,O). A run-time enforcement shield is a controller which takes (I,O) (coming from SSE) as its input, an
Externí odkaz:
http://arxiv.org/abs/1909.08541
Autor:
Pandya, Paritosh K., Wakankar, Amol
This paper investigates the synthesis of robust controllers from logical specification of regular properties given in an interval temporal logic QDDC. Our specification encompasses both hard robustness and soft robustness. Here, hard robustness guara
Externí odkaz:
http://arxiv.org/abs/1905.11157
In reactive controller synthesis, a number of implementations (controllers) are possible for a given specification because of the incomplete nature of specification. To choose the most desirable one from the various options, we need to specify additi
Externí odkaz:
http://arxiv.org/abs/1903.03991
Publikováno v:
Logical Methods in Computer Science, Volume 16, Issue 3 (September 8, 2020) lmcs:5206
We study two extensions of FO2[<], first-order logic interpreted in finite words, in which formulas are restricted to use only two variables. We adjoin to this language two-variable atomic formulas that say, "the letter $a$ appears between positions
Externí odkaz:
http://arxiv.org/abs/1902.05905
This paper investigates Kamp-like and B\"uchi-like theorems for 1-clock Alternating Timed Automata (1-ATA) and its natural subclasses. A notion of 1-ATA with loop-free-resets is defined. This automaton class is shown to be expressively equivalent to
Externí odkaz:
http://arxiv.org/abs/1802.02514
Autor:
Pandya, Paritosh K., Wakankar, Amol
Publikováno v:
In Information and Computation May 2022 285 Part B