Extraction of parasitic and channel resistance components in FinFETs using TCAD tools

Autor: Narayanan, Sudarshan, Banghart, Edmund, Zeitzoff, Peter, Korablev, Konstantin, Pandey, Shesh Mani, Gendron-Hansen, Amaury, Benistant, Francis

Publikováno v: In Solid State Electronics September 2016 123:44-50

Impact of additional LDD rapid thermal annealing on submicron n-MOSFETs

Autor: V.K.W. Leong, Qian Wensheng, F. Benistant, S. Manju, Wang Yuwen, S. Chu, Pandey Shesh Mani, Li Yisuo

Publikováno v: Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI.

An additional NLDD Rapid Thermal Annealing (RTA) had been implemented in thin-gate and thick-gate NMOS transistors. The threshold voltage (Vt) distribution at different gate lengths was investigated for devices with and without NLDD RTA. Lower roll-u

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::124cfce02bc591641e98c6d04993a586
https://doi.org/10.1109/asmc.2003.1194498

Investigation of performance limiting factors of sub-10nm III-V FinFETs.

Autor: Feng, Peijie, Narayanan, Sudarshan, Pandey, Shesh Mani, Sahu, Bhagawan, Benistant, Francis, Towie, Ewan, Alexander, Craig, Amoroso, Salvatore M., Asenov, Asen

Publikováno v: EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop & International Conference on Ultimate Integration on Silicon; 2015, p105-108, 4p

Impact of additional LDD rapid thermal annealing on submicron n-MOSFETs.

Autor: Qian Wensheng, Leong, V.K.W., Wang Yuwen, Li Yisuo, Pandey Shesh Mani, Manju, S., Benistant, F., Chu, S.

Publikováno v: Advanced Semiconductor Manufacturing Conference & Workshop, 2003 IEEEI/SEMI; 2003, p234-237, 4p

Methodology to achieve planar technology-like ESD performance in FINFET process.

Autor: Lee, Jian-Hsing, Prabhu, Manjunatha, Korablev, Konstantin, Singh, Jagar, Natarajan, Mahadeva Iyer, Pandey, Shesh Mani

Publikováno v: 2015 IEEE International Reliability Physics Symposium; 2015, p00-3F.3.6, 0p