Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Pak-Kim Lau"'
Autor:
Chih-Wei Yao, Wanghua Wu, Lei Chen, Chengkai Guo, Sang Won Son, Zhanjun Bai, Pak-Kim Lau, Thomas Byunghak Cho, Pei-Yuan Chiang
Publikováno v:
IEEE Journal of Solid-State Circuits. 56:3756-3767
This work presents a 6-GHz low-jitter and high figure-of-merit (FoM) fractional-N phase-locked loop (PLL). It uses a digital-to-time converter (DTC)-based sampling PLL architecture. To achieve ultra-low jitter in fractional-N mode, a phase detector r
Autor:
Ashutosh Verma, Venu Bhagavatula, Amitoj Singh, Wanghua Wu, Hariharan Nagarajan, Pak-Kim Lau, Xiaohua Yu, Omar Elsayed, Ajaypat Jain, Anirban Sarkar, Fan Zhang, Che-Chun Kuo, Patrick McElwee, Pei-Yuan Chiang, Chengkai Guo, Zhanjun Bai, Tienyu Chang, Abishek Mann, Andreas Rydin, Xingliang Zhao, Jeiyoung Lee, Daeyoung Yoon, Chih-Wei Yao, Siuchuang Ivan Lu, Sang Won Son, Thomas B. Cho
Publikováno v:
2022 IEEE International Solid- State Circuits Conference (ISSCC).
Autor:
Chih-Wei Yao, Sang Won Son, Lei Chen, Thomas Byunghak Cho, Chengkai Guo, Wanghua Wu, Pei-Yuan Chiang, Pak-Kim Lau
Publikováno v:
ISSCC
A local oscillator (LO) for 5G new radio requires sub-100fs rms jitter to support 64-OAM and $2\times2$ MIMO under non-ideal channel conditions [1]. Although fractional-N phase-locked loops (PLLs) employing digital-to-time converters (DTCs) and sampl
Publikováno v:
CICC
A low-power passive switched-capacitor finite-impulse response equalizer with six time-interleaved channels has been fabricated in 0.35/spl mu/m CMOS. Nonlinear parasitic capacitance scales the equalized output but does not affect the zero locations
Publikováno v:
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005; 2005, p633-636, 4p