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Autor:
Paikaray, Bijay
Current day processors employ multi-level cache hierarchy with one or two levels of private caches and a shared last-level cache (LLC). An efficient cache replacement policy at LLC is essential for reducing the off-chip memory transfer as well as con
Externí odkaz:
http://arxiv.org/abs/1307.6406
Autor:
Paikaray, Bijay
The rapid improvement of the mobile generations was for the purpose of supporting as many mobile devices as possible that could benefit the users at anytime and anywhere in terms of common practical applications such as internet access, video-on-dema
Externí odkaz:
http://arxiv.org/abs/1209.4968
Due to the huge difference in performance between the computer memory and processor, the virtual memory management plays a vital role in system performance. A Cache memory is the fast memory which is used to compensate the speed difference between th
Externí odkaz:
http://arxiv.org/abs/1107.4851
Autor:
Mishra, Biswaranjan, Gopal, Kakita Murali, Patnaik, Srikant, Paikaray, Bijay Kumar, Pramanik, Jitendra
Publikováno v:
AIP Conference Proceedings; 2023, Vol. 2981 Issue 1, p1-8, 8p
Autor:
Paikaray, Bijay Kumar, Nayak, Suvendu Kumar, Pramanik, Jitendra, Thapa, Rishi, Swain, Debabala, Samal, Abhaya Kumar
Publikováno v:
AIP Conference Proceedings; 2023, Vol. 2981 Issue 1, p1-6, 6p
Autor:
Nayak, Sasmita Kumari, Pattnaik, Satyajit, Siddique, Mohammed, Garanayak, Mamata, Paikaray, Bijay Kumar
Publikováno v:
International Journal of Business Continuity and Risk Management; 2024, Vol. 14 Issue: 4 p371-391, 21p
Publikováno v:
International Journal of Internet Manufacturing and Services; 2024, Vol. 10 Issue: 4 p346-376, 31p
Autor:
Nayak, Sushree Sangita, Mohapatra, Aswini Kumar, Maharana, Srikanta, Mishra, Biswaranjan, Pattanaik, Bijay Kishor Shishir Sekhar, Paikaray, Bijay Kumar
Publikováno v:
International Journal of Computational Biology and Drug Design; 2024, Vol. 16 Issue: 2 p147-166, 20p
Publikováno v:
International Journal of Web and Grid Services; 2024, Vol. 20 Issue: 2 p159-187, 29p