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pro vyhledávání: '"Padmaraj Singh"'
Publikováno v:
ACM Transactions on Design Automation of Electronic Systems. 17:1-19
Multicore Register Transfer Level (RTL) model simulations are indispensable in exposing subtle memory subsystem bugs. Validating memory consistency, coherency, and atomicity is a crucial design verification task. Random MultiProcessor (MP) test gener
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 15:495-504
Microprocessor designs are increasingly moving towards multiple cores on a single die. Validating memory consistency, coherency, ordering, and atomicity is crucial. X86 microprocessors are prevalent at most levels of computing. Thus, new x86 micropro
Autor:
David L. Landis, Padmaraj Singh
Publikováno v:
MTV
Full-chip simulation of multicore designs is an important element in the design verification cycle of a Chip Multiprocessor (CMP). Random tests are typically applied to the Multiprocessor (MP) in order to stimulate unexercised states of the machine.
Publikováno v:
MTV
Validation of precise interrupts on a modern pipelined processor is a non-trivial task. The common approach of asserting external interrupts at random test points offers insufficient coverage, and exhaustive simulation under all pipeline conditions i
Conference
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