Usefulness and effectiveness of HW and SW protection mechanisms in a processor-based system

Autor: Regis Leveugle, Michele Portolan, P. Vanhauwaert, Philippe Roche

Publikováno v: IEEE International Conference on Electronics, Circuits and Systems (ICECS'08)
IEEE International Conference on Electronics, Circuits and Systems (ICECS'08), Sep 2008, Saint Julians, Malta. pp.113-116
HAL
ICECS

ISBN : 978-1-4244-2182-4; International audience; Fault-injection based dependability analysis has proved to be an efficient mean to predict the behavior of a circuit in presence of faults. Emulation-based approaches enable fast and flexible analyses

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::356167e98625274e1291017d6db14739
https://hal.archives-ouvertes.fr/hal-00322962

Software BIST capabilities of a symmetric cipher

Autor: Regis Leveugle, C. Excoffon, Paolo Maistri

Publikováno v: ICECS
International Conference on Electronics, Circuits and Systems (ICECS)
International Conference on Electronics, Circuits and Systems (ICECS), Sep 2008, Saint Julians, Malta. pp.414-417

ISBN 978-1-4244-2182-4; International audience; Cryptographic devices have to be fully testable in order to ensure proper functionalities. On the other hand, security requirements restrict the use of some testing techniques, such as scan chains. Buil

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d0b57e8898ae85c26c7e0119a80582e6
https://doi.org/10.1109/icecs.2008.4674878

Formal Verification of the Communications in Networks on Chips

Autor: Helmy, A., Pierre, Laurence

Publikováno v: 2ème Colloque du GdR SoC-SiP
2ème Colloque du GdR SoC-SiP, Jun 2008, Paris, France

Most of today's SoC's (Systems on Chips) are made of manufactured IP's interconnected through complex networks on chips (NoCs). We propose a generic NoC model, GeNoC, as a formal reference for the specification, formal verification, and simulation at

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::42ef16f663f6716052e73bfb3df175c5
https://hal.archives-ouvertes.fr/hal-00323015

Assertion-Based Design with Horus

Autor: Katell Morin-Allory, Dominique Borrione, Y. Oddos

Publikováno v: MEMOCODE
International Conference on Formal Methods and Models for Codesign (MEMOCODE'2008)
International Conference on Formal Methods and Models for Codesign (MEMOCODE'2008), Jun 2008, Anaheim,CA, United States. pp.75-76, ⟨10.1109/MEMCOD.2008.4547691⟩

ISBN : 978-1-4244-2417-7; International audience; The Horus tool, based on formally proven correct methods, provides a unified support to assertion-based design, between the specification and the test phases. Given a set of logical and temporal prope

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5913e782d105b44e1b50431ba306f241
https://doi.org/10.1109/memcod.2008.4547691

AHMOSE: Towards a Circuit Level Solution for Process Variability

Autor: Yahya, E., Renaudin, Marc

Publikováno v: Design, Automation and Test in Europe Conference (DATE'08)
Design, Automation and Test in Europe Conference (DATE'08), Mar 2008, Munich, Germany

actes sur CD; International audience; Asynchronous circuits are increasingly proposed as an efficient circuit-level solution for Process Variability. Asynchronous circuits are self timed, which gives them the opportunity to be immune against all vari

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::53ea51c8d1b9efa0d1bcbb5345bbecc1
https://hal.archives-ouvertes.fr/hal-00323011