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A 2.5 Gb/s ATM add-drop unit for B-ISDN based on a GaAs LSI

Autor: P.S. Lassen, J.K. Madsen

Publikováno v: IEEE Journal of Solid-State Circuits. 31:1400-1405

This paper describes the design and implementation of a high-speed GaAs asynchronous transfer mode (ATM) mux-demux ASIC (AMDA) which is the core LSI circuit in a high-speed ATM add-drop unit (ADU). This unit is used in a new distributed ATM multiplex

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::5e9b29d8f98cc1a50e7c764298d68818
https://doi.org/10.1109/4.540047

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GaAs VLSI implementation of a 2.5 Gb/s ATM label translator

Autor: P.S. Lassen, I. Moussa

Publikováno v: GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996.

Routing tables for communication networks can be designed using several approaches, including table look-up, content-addressable Memory (CAM), hashing, and tries. This paper presents a GaAs VLSI implementation of an efficient table lookup algorithm f

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::7b438b3d204a036499aaf8731bb6a75a
https://doi.org/10.1109/gaas.1996.567649

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VLSI implementation of a fairness ATM buffer system

Autor: L. Dittman, P.S. Lassen, J.V. Nielsen, J.K. Madsen

Publikováno v: Nielsen, J V, Dittmann, L, Madsen, J K & Lassen, P S 1996, VLSI implementation of a fairness ATM buffer system . in Conference Record of IEEE International Conference on Communications : Converging Technologies for Tomorrow's Applications . vol. Volume 2, IEEE, pp. 681-686, IEEE International Conference on Communications 1996, Dallas, Texas, United States, 23/06/1996 . https://doi.org/10.1109/ICC.1996.541268

This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing i

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::eebdc94fb23f745c98510c4d74155bad
https://doi.org/10.1109/icc.1996.541268

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A 2.5 gb/s GaAs ATM Mux Demux ASIC

Autor: J.K. Madsen, P.S. Lassen

Publikováno v: Madsen, J K & Lassen, P S 1995, A 2.5 gb/s GaAs ATM Mux Demux ASIC . in Technical Digest of the 17th Annual IEEE Gallium Arsenide Integrated Circuit Symposium . IEEE, pp. 43-46, 17th Annual IEEE Gallium Arsenide Integrated Circuit Symposium, San Diego, CA, United States, 28/10/1995 . https://doi.org/10.1109/GAAS.1995.528957

This paper describes the design and implementation of a high speed GaAs ATM Mux Demur ASIC (AMDA) which is the key element in a high speed ATM Add-Drop unit. This unit is used in a new distributed ATM multiplexing-demultiplexing architecture for broa

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8baa5246fe3fd9d43988a00842a80aed
https://doi.org/10.1109/gaas.1995.528957

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Ultralow-power GaAs MESFET MSI circuits using two-phase dynamic FET logic

Autor: S.I. Long, P.S. Lassen, K.R. Nary

Publikováno v: Lassen, P S, Long, S I & Nary, K R 1993, ' Ultralow-power GaAs MESFET MSI circuits using two-phase dynamic FET logic ', I E E E Journal of Solid State Circuits, vol. 28, no. 10, pp. 1038-1045 . https://doi.org/10.1109/4.237519

Two-phase dynamic FET logic (TDFL) gates are used in GaAs MESFET MSI circuits to implement very low power 4-b ripple carry adders and a variable modulus (2 to 31) prescaler. Operation of the adders is demonstrated at 500 MHz with an associated power

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::40de780f2e3e78570b04e66e3bd5c2f7
https://orbit.dtu.dk/en/publications/6a9282f1-731b-453a-aa4c-8622a999da5d

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