Zobrazeno 1 - 10
of 400
pro vyhledávání: '"P.K. Lala"'
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 54:2696-2705
Carry-select adders are one of the faster types of adders. This paper proposes a scheme that encodes the sum bits using two-rail codes; the encoded sum bits are then checked by self-checking checkers. The multiplexers used in the adder are also total
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::24c2700b512dc3306b72bf525eb694ce
https://doi.org/10.1109/tcsi.2007.910537
https://doi.org/10.1109/tcsi.2007.910537
Publikováno v:
Microelectronics Journal. 37:353-362
In recent years there has been a significant growth of interest in exploiting the principles of biological processes to create powerful methodologies for solving computational problems. This paper discusses how these features have been exploited in d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::544d06ad6114544082ced9a5b59cff0b
https://doi.org/10.1016/j.mejo.2005.05.025
https://doi.org/10.1016/j.mejo.2005.05.025
Publikováno v:
IEEE Transactions on Instrumentation and Measurement. 55:406-414
Conventional digital circuits dissipate a significant amount of energy because bits of information are erased during the logic operations. Thus, if logic gates are designed such that the information bits are not destroyed, the power consumption can b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1db6487325d72636b2be6d1ca9bbd629
https://doi.org/10.1109/tim.2006.870319
https://doi.org/10.1109/tim.2006.870319
Autor:
A.L. Burress, P.K. Lala
Publikováno v:
IEEE Transactions on Instrumentation and Measurement. 52:1391-1398
Field programmable gate arrays (FPGAs) are being increasingly used in many systems including intelligent instrumentation. A synthesis algorithm for generating self-checking combinational logic for implementation on look-up table based FPGAs is presen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dc7d2a37db794875583322f2da160297
https://doi.org/10.1109/tim.2003.818545
https://doi.org/10.1109/tim.2003.818545
Autor:
P.K. Lala, B. Kiran Kumar
Publikováno v:
Journal of Electronic Testing. 19:523-535
The use of very deep submicron technology makes VLSI-based digital systems more susceptible to transient or soft errors, and thus compromises their reliability. This paper proposes an architecture inspired by the human immune system that allows toler
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0ded989b658bd9ebe362e27c45834a7f
https://doi.org/10.1023/a:1025169829818
https://doi.org/10.1023/a:1025169829818
Akademický článek
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Autor:
Alvernon Walker, P.K. Lala
Publikováno v:
VLSI Design, Vol 12, Iss 4, Pp 527-536 (2001)
This paper proposes a logic cell that can be used as a building block for Self-checking FPGAs. The proposed logic cell consists of two 2-to-1 multiplexers, three 4-to-1 multiplexers and a D flip-flop. The cell has been designed using Differential Cas
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3d929caa228b373e024b600a71101b52
https://doaj.org/article/bcc3950eeefe4d41b27ef461521c26ba
https://doaj.org/article/bcc3950eeefe4d41b27ef461521c26ba
Publikováno v:
VLSI Design, Vol 7, Iss 2, Pp 151-161 (1998)
A technique for designing totally self-checking (TSC) FCMOS (Fully Complementary MOS) designs for multiple faults is presented in this paper. The existing techniques for self checking design consider only single faults, and suffer from high silicon a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3c10f5847ca03dbda18de2695dbc6d00
https://doaj.org/article/3eb3c841301e42b789855568f9040a25
https://doaj.org/article/3eb3c841301e42b789855568f9040a25
Autor:
P.K. Lala, D. A. Pierce
Publikováno v:
Journal of Electronic Testing. 9:279-294
A technique for designing efficient checkers for conventional Berger code is proposed in this paper. The check bits are derived by partitioning the information bits into two blocks, and then using an addition array to sum the number of 1's in each bl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5bb75b4215a369588cde4b29e0facf1c
https://doi.org/10.1007/bf00134692
https://doi.org/10.1007/bf00134692
Autor:
Fadi Busaba, P.K. Lala
Publikováno v:
Journal of Electronic Testing. 5:19-28
This article presents novel input and output encoding techniques such that the resulting circuit is bidirectional error-free. The circuit can be fully optimized and any types of gates can be used. These schemes are used to design the functional part
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e9776b674082a145900688daf11f9589
https://doi.org/10.1007/bf00971960
https://doi.org/10.1007/bf00971960