Zobrazeno 1 - 10
of 36
pro vyhledávání: '"P.C.T. Roberts"'
Autor:
H.B. Barber, H.H. Barrett, E.L. Dereniak, N.E. Hartsough, D.L. Perry, M.M. Rogulski, J.M. Woolfenden, E.T. Young, P.C.T. Roberts
Publikováno v:
IEEE Conference on Nuclear Science Symposium and Medical Imaging.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d50f8b3e2946adf7a5061b65d3fc7345
https://doi.org/10.1109/nssmic.1992.301068
https://doi.org/10.1109/nssmic.1992.301068
Publikováno v:
IEEE Transactions on Electron Devices. 22:289-293
A technique for fabricating charge-coupled devices with submicron gaps is described. The method relies on a "shadowing" effect produced by oblique deposition of the metal in an otherwise standard vacuum evaporation process. The biggest advantage of t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1b79d9743a77176e7bc9b1aba79af28b
https://doi.org/10.1109/t-ed.1975.18120
https://doi.org/10.1109/t-ed.1975.18120
Autor:
G. Y. Lee, K.W. Lee, S.A. Hanka, C.A. Arsenault, Barry K. Gilbert, Andrzej Peczalski, Michael Shur, M.J. Helix, S.A. Jamison, W.R. Betten, S.M. Karwoski, Roderick D. Nelson, P.C.T. Roberts, Tho T. Vu, S.K. Swanson, G.M. Lee, P.J. Vold, B.A. Naused
Publikováno v:
IEEE Journal of Solid-State Circuits. 23:224-238
Using GaAs self-aligned gate MESFETs, low-power logic circuits have been demonstrated for both depletion-mode (D-mode) Schottky-diode FET logic (SDFL) and enhancement/depletion-mode (E/D-mode) direct-coupled FET logic (DCFL). Propagation delays of 1.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c5554bdd2e1e61dd1cd30234aea0471e
https://doi.org/10.1109/4.283
https://doi.org/10.1109/4.283
Publikováno v:
IEEE Transactions on Electron Devices. 32:987-992
Techniques which allow us to determine the series source, drain, and gate resistances and the electron saturation velocity of ion-implanted GaAs FET's are described. These techniques are based on the "end" resistance measurements. The theory of this
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::77329010183ba44559ba0b9d9aef94c6
https://doi.org/10.1109/t-ed.1985.22058
https://doi.org/10.1109/t-ed.1985.22058
Autor:
J.D.E. Beynon, P.C.T. Roberts
Publikováno v:
Solid-State Electronics. 16:221-227
Leakage currents in phosphorus-gettered (111) silicon have been studied at room temperature using a MOS gate-controlled diode structure. The leakage current and the gate-substrate capacitance have each been measured as a function of gate voltage for
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::25b2ab93547e0ca26acbd45ce86cf8dd
https://doi.org/10.1016/0038-1101(73)90032-4
https://doi.org/10.1016/0038-1101(73)90032-4
Autor:
J.D.E. Beynon, P.C.T. Roberts
Publikováno v:
Solid-State Electronics. 17:403-404
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3190ae3c92d511e1198058df3e3612c5
https://doi.org/10.1016/0038-1101(74)90132-4
https://doi.org/10.1016/0038-1101(74)90132-4
Publikováno v:
Proceedings of the Institution of Electrical Engineers. 122:1089
Measurements of charge-transfer inefficiency have been carried out using 3-phase surface-channel c.c.d.s fabricated on (100) and (111) orientation subtrates. The occurrence of two loss mechanisms, namely backward-flow loss and surface-state loss, is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a6e338cd30e94a2ef726f4d91e703683
https://doi.org/10.1049/piee.1975.0267
https://doi.org/10.1049/piee.1975.0267
Publikováno v:
Electronics Letters. 13:93
Large variations have been observed between pulsed capacitor relaxation-time measurements made on samples which have received identical processing. This effect has been studied with 1 mm-diameter m.o.s. capacitors on (100)-orientation Czochralski sil
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3986a3afa2437f80a2582a5ca2f10a88
https://doi.org/10.1049/el:19770065
https://doi.org/10.1049/el:19770065
Publikováno v:
Proceedings of the Institution of Electrical Engineers. 123:389
An analysis of surface-state trapping loss in surface-channel c.c.d.s has been carried out. By calculating the areas under the transfer gates occupied by different sized charge packets it has been shown that the edge effect is the dominant loss mecha
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::715801d87fce3945e7785b6020dd2a10
https://doi.org/10.1049/piee.1976.0088
https://doi.org/10.1049/piee.1976.0088
Publikováno v:
IEE Journal on SolidState and Electron Devices. 1:73
The effects of depletion-capacitance-induced distortion in split-electrode surface-channel c.c.d. transversal filters are analysed. Two standard charge-inputting techniques (the `diode cut off? and `fill and spill? schemes) and the two usual tapping
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::94a176e7f4680ff5487914152ba032a7
https://doi.org/10.1049/ij-ssed.1977.0008
https://doi.org/10.1049/ij-ssed.1977.0008