Zobrazeno 1 - 10
of 42
pro vyhledávání: '"P. Vandervoorn"'
Autor:
R. Yavatkar, Chang-Tsung Fu, Taehwan Kim, Hasnain Lakdawala, Ajay Balankutty, Chun Lee, Satoshi Suzuki, Hyung-Jin Lee, Rahul Limaye, P. Vandervoorn, Brent Carlton, Erkan Alpman, S. Ramamurthy, Jad B. Rizk, Durgesh Srivastava, Krishnamurthy Soumyanath, Duster Jon Sweat, Stefano Pellerano, Tan Yulin, C.-H. Jan, Marian Verhelst, Mark A. Schaecher, Ashoke Ravi, Satish Venkatesan, Khoa Minh Nguyen, Hyung Seok Kim
Publikováno v:
IEEE Journal of Solid-State Circuits. 48:91-103
An t 86 standard operating system compliant System-on-Chip (SoC) with a dual core ATOM processor and a custom interconnect fabric to enable modular design is presented. The 32 nm SoC includes integrated PCI-e Gen 2, DDR3, legacy I/O, voltage regulato
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cd0b2f7ae64dfb70741acbc72df3c6da
https://doi.org/10.1109/jssc.2012.2222812
https://doi.org/10.1109/jssc.2012.2222812
Autor:
J. Lee, P. Bai, T. Leo, S. K.-Y. Shi, P. Vandervoorn, D. Ingerly, L. Rockford, Ramaswamy Rahul, Y.-W. Chen, Nidhi Nidhi, F. Al-Amoody, M. Jang, K. Byon, T. Rana, Curtis Tsai, A. Zainuddin, C. Quincy, Eric Karl, L. Yang, Hafez Walid M, Chetan Prasad, C. Petersburg, Olac-Vaw Roman W, K. Komeyli, A. Kumar, Chang Hsu-Yu, Anand Subramaniam, N. L. Dias, Tsung-Yuan Chang, H. Kilambi, K. Phoa, Pei-Chi Liu, Chen-Guan Lee, C.-H. Jan
Publikováno v:
VLSIC
A leading edge 14 nm SoC platform technology based upon the 2nd generation Tri-Gate transistor technology [5] has been optimized for density, low power and wide dynamic range. 70 nm gate pitch, 52 nm metal pitch and 0.0499 um2 HDC SRAM cells are the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3ad023e07edda7779db811903bcb46fb
https://doi.org/10.1109/vlsic.2015.7231380
https://doi.org/10.1109/vlsic.2015.7231380
Autor:
Ian R. Post, Kaizad Mistry, P. Vandervoorn, Chetan Prasad, A. Schmitz, Paul A. Packan, Dhruv Singh, B. Niu, M. Agostinelli, Daniel Pantuso, P. Bai, S. Ramey, Sanjay Natarajan, Travis Eiles, J. Thomas, Sell Bernhard, J. Hicks, Lei Jiang, C. Auth, Chia-Hong Jan, S. Suthram, Curtis Tsai
Publikováno v:
2013 IEEE International Reliability Physics Symposium (IRPS).
This paper describes various measurements on self-heat performed on Intel's 22nm process technology, and outlines its reliability implications. Comparisons to thermal modeling results and analytical data show excellent matching.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bdf10a9b4063c91c8c77e92ca1ae6b46
https://doi.org/10.1109/irps.2013.6532036
https://doi.org/10.1109/irps.2013.6532036
Autor:
K. Komeyli, H. Tashiro, J.-Y. Yeh, Joodong Park, C. Staus, M. Kang, M. Jang, Uddalak Bhattacharya, P. Bai, Abdur Rahman, Chia-Hong Jan, Kinyip Phoa, Curtis Tsai, P. Vandervoorn, Ruth A. Brain, L. Yang, G. Curello, Nidhi Nidhi, S.-J. Choi, G. Gupta, Hafez Walid M, L. Pan, T. Leo
Publikováno v:
2012 International Electron Devices Meeting.
A leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time. Low standby power and high voltage transistors exploiting the superior short channel control, < 65mV/dec subthreshold slope and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::65cbc6de11013a48dd62c1a5522bbbc4
https://doi.org/10.1109/iedm.2012.6478969
https://doi.org/10.1109/iedm.2012.6478969
Autor:
Brent Carlton, Marian Verhelst, Tan Yulin, Ajay Balankutty, Krishnamurthy Soumyanath, Erkan Alpman, Stefano Pellerano, Duster Jon Sweat, Satish Venkatesan, Rahul Limaye, Hasnain Lakdawala, Sunder Ramamurthy, Chia-Hong Jan, Hyung Seok Kim, Chang-Tsung Fu, Mark A. Schaecher, P. Vandervoorn, Tong Kim, Chun Lee, Hyung-Jin Lee, Jad B. Rizk, Durgesh Srivastava, Satoshi Suzuki
Publikováno v:
ISSCC
Embedded PC applications are growing, driven by their cost, performance and software compatibility. The SoC described in this work is a unique device designed for rapid integration and customization for specific market segments. A rich multi-source I
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dc91f7b6bc7df1b484d62a3c8d0c81d8
https://doi.org/10.1109/isscc.2012.6176879
https://doi.org/10.1109/isscc.2012.6176879
Autor:
S. Mudanai, Krishnamurthy Soumyanath, J. Lin, Abdur Rahman, Curtis Tsai, W.-K. Shin, Y-L Lu, Mohammed A El-Tanani, P. Bai, H. Tashiro, U. Jalan, Joodong Park, P. Vandervoorn, L. Janbay, M. Agostinelli, Hasnain Lakdawala, Chia-Hong Jan, Jad B. Rizk, M. Kang, Hafez Walid M, H. Deshpande, J.-Y. Yeh
Publikováno v:
2010 International Electron Devices Meeting.
The impact of silicon technology scaling trends and the associated technological innovations on RF CMOS device characteristics are examined. The application of novel strained silicon and high-k/metal gate technologies not only benefits digital system
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f8d7f897ac633830ba8e7f473b084cb5
https://doi.org/10.1109/iedm.2010.5703431
https://doi.org/10.1109/iedm.2010.5703431
Autor:
Mohammed A El-Tanani, H. Deshpande, Krishnamurthy Soumyanath, S. Mudanai, Abdur Rahman, Hafez Walid M, M. Agostinelli, Hasnain Lakdawala, U. Jalan, J.-Y. Yeh, L. Rockford, Stewart S. Taylor, Kwang-Jin Koh, P. Vandervoorn, L. Janbay, H. Tashiro, L. Yang, S.-J. Choi, M. Kang, P. Bai, Curtis Tsai, J. Lin, Jad B. Rizk, K. Phoa, Hongtao Xu, J. Xu, K. Komeyli, Nick Lindert, J. Yip, G. Sacks, Ian A. Young, C.-H. Jan, G. Curello, Joodong Park
Publikováno v:
2010 Symposium on VLSI Technology.
A 32nm RF SOC technology is developed with high-k/metal-gate triple-transistor architecture simultaneously offering devices with high performance and very low leakage to address advanced RF/mobile communications markets. A high performance NMOS achie
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1b6b5e40107c1a394af62bae286b1d46
https://doi.org/10.1109/vlsit.2010.5556201
https://doi.org/10.1109/vlsit.2010.5556201
Autor:
J.-Y. Yeh, M. Prince, L. Rockford, Kevin Zhang, J. Lin, Pramod Kolar, B. Landau, H. Tashiro, Ian R. Post, Seung Hwan Lee, N. Lazo, A. Schmitz, S. Gannavaram, P. Bai, P. Vandervoorn, Zhanping Chen, S. Ma, J. Xu, G. Curello, K. Komeyli, L. Yang, Nick Lindert, J. Rizk, C.-H. Jan, S.-J. Choi, J. Yip, Yuegang Zhang, M. Agostinelli, Joodong Park, Curtis Tsai, Hafez Walid M, A. Lake, K. Phoa, N. Pradhan, H. Deshpande, C. Meining, M. Kang, L. McGill, A. Paliwal, G. Sacks, T. Leo, M. Buehler, U. Jalan, Abdur Rahman
Publikováno v:
2009 IEEE International Electron Devices Meeting (IEDM).
A leading edge 32nm high-k/metal gate transistor technology has been optimized for SoC platform applications that span a wide range of power, performance, and feature space. This technology has been developed to be modular, offering mix-and-match tra
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::93c5c78a71e8bd1f995efb0a3568b699
https://doi.org/10.1109/iedm.2009.5424258
https://doi.org/10.1109/iedm.2009.5424258
Autor:
V. Souw, Michael K. Harper, H. Mariappan, P. Vandervoorn, K. Tone, C. Auth, G. Glass, Timothy E. Glassman, Kaizad Mistry, A. Thompson, S. Jaloviar, Tahir Ghani, M. Lu, Nadia M. Rahhal-Orabi, Jason Klaus, J. Sandford, Christopher J. Wiegand, B. Norris, F. Tambwe, T. Troeger, D. Lavric, Pushkar Ranade, Michael L. Hattendorf, Annalisa Cappellani, Subhash M. Joshi, J.-S. Chun, J. Wiedemer, A. Dalis, K. Kuhn, P. Hentges, D. Towner, Charles H. Wallace, Alison Davis, Lucian Shifren
Publikováno v:
2008 Symposium on VLSI Technology.
Two key process features that are used to make 45 nm generation metal gate + high-k gate dielectric CMOS transistors are highlighted in this paper. The first feature is the integration of stress-enhancement techniques with the dual metal-gate + high-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::61d8f22f52ce9f6ca3a2f66713d2fefa
https://doi.org/10.1109/vlsit.2008.4588589
https://doi.org/10.1109/vlsit.2008.4588589
Autor:
D. Ingerly, K. Zawadzki, R. James, C. Allen, Kaizad Mistry, B. Beattie, W. Han, Lucian Shifren, J. Sebastian, M. Bost, C. Kenyon, Pete Smith, D. Simon, D. Hanken, G. Ding, J. Maiz, C. Thomas, L. Pipes, Annalisa Cappellani, Pulkit Jain, J. He, M. Hattendorf, T. Troeger, Subhash M. Joshi, R. Chau, L. Jong, D. Parsons, Daniel B. Bergstrom, B. Mclntyre, Tahir Ghani, T. Reynolds, Swaminathan Sivakumar, J. Hicks, S. Williams, C. H. Choi, K. Kuhn, C. Auth, Pushkar Ranade, K. Fischer, M. Buehler, M. Brazier, M. Prince, J. Seiple, Chetan Prasad, J. Neirynck, P. Vandervoorn, Huichu Liu, J. Sandford, S. Pae, R. Huessner, K. Lee, C. Parker, P. Moon, R. Grover
Publikováno v:
2007 IEEE International Electron Devices Meeting.
A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::42030b74ebfeb3f32e324cf5cac0d4d8
https://doi.org/10.1109/iedm.2007.4418914
https://doi.org/10.1109/iedm.2007.4418914