Zobrazeno 1 - 10
of 74
pro vyhledávání: '"Oskar Baumgartner"'
Autor:
Josip Bobinac, Tobias Reiter, Julius Piso, Xaver Klemenschits, Oskar Baumgartner, Zlatan Stanojevic, Georg Strof, Markus Karner, Lado Filipovic
Publikováno v:
Micromachines, Vol 14, Iss 3, p 665 (2023)
It is becoming quite evident that, when it comes to the further scaling of advanced node transistors, increasing the flash memory storage capacity, and enabling the on-chip integration of multiple functionalities, “there’s plenty of room at the t
Externí odkaz:
https://doaj.org/article/4d8f0a93fc884206bf58c9edfca24fad
Autor:
Krishna K. Bhuwalka, Hao Wu, Wenbo Zhao, Gerhard Rzepa, Oskar Baumgartner, Francis Benistant, Yijian Chen, Changze Liu
Publikováno v:
IEEE Transactions on Electron Devices. 69:4088-4094
Autor:
Mischa Thesberg, Md Nur K. Alam, Brecht Truijen, Ben Kaczer, Philippe J. Roussel, Zlatan Stanojevic, Oskar Baumgartner, Franz Schanovsky, Markus Karner, Hans Kosina
Publikováno v:
IEEE Transactions on Electron Devices. 69:3105-3112
Autor:
C. Kernstock, Zlatan Stanojevic, Chen-Ming Tsai, Ferdinand Mitterbauer, Oskar Baumgartner, Georg Strof, Markus Karner
Publikováno v:
IEEE Transactions on Electron Devices. 68:5400-5406
We present an in-depth discussion on the subband Boltzmann transport (SBTE) methodology, its evolution, and its application to the simulation of nanoscale MOSFETs. The evolution of the method is presented from the point of view of developing a commer
Autor:
Gerhard Rzepa, Krishna K. Bhuwalka, Oskar Baumgartner, Daniele Leonelli, Hui-Wen Karner, Franz Schanovsky, Christian Kernstock, Zlatan Stanojevic, Hao Wu, Francis Benistant, Changze Liu, Markus Karner
Publikováno v:
2022 International Electron Devices Meeting (IEDM).
Autor:
Gautam Gaddemane, Krishna K. Bhuwalka, Philippe Matagne, Gerhard Rzepa, Maarten Van de Put, Sybren Santermans, Oskar Baumgartner, Hao Wu, Geert Hellings
Publikováno v:
ESSDERC 2022 - IEEE 52nd European Solid-State Device Research Conference (ESSDERC).
Autor:
Lado Filipovic, Oskar Baumgartner, Xaver Klemenschits, Julius Piso, Josip Bobinac, Tobias Reiter, Georg Strof, Gerhard Rzepa, Zlatan Stanojevic, Markus Karner
Publikováno v:
Solid-State Electronics. 199:108527
Autor:
Zlatan Stanojevic, G. Strof, F. Mitterbauer, Markus Karner, Oskar Baumgartner, H. W. Karner, Franz Schanovsky, C. Kernstock, Gerhard Rzepa
Publikováno v:
2021 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
Variability increases with downscaling, making it a vital component in the assessment of upcoming technologies. We use a variability-aware DTCO flow, which seamlessly integrates accurate TCAD simulations with industry-proven SPICE solutions. The impa
Autor:
A. Bosio, Arnaud Poittevin, Thomas Mikolajick, S. Le Beux, Chhandak Mukherjee, Jens Trommer, Ian O'Connor, Cristell Maneux, Guilhem Larrieu, Zlatan Stanojevic, Oskar Baumgartner
Publikováno v:
EuroSOI-ULIS
EuroSOI-ULIS, Sep 2021, Caen, France
EuroSOI-ULIS, Sep 2021, Caen, France. ⟨10.1109/EuroSOI-ULIS53016.2021.9560180⟩
EuroSOI-ULIS, Sep 2021, Caen, France
EuroSOI-ULIS, Sep 2021, Caen, France. ⟨10.1109/EuroSOI-ULIS53016.2021.9560180⟩
To sustain transistor scaling beyond lateral 7nm devices, gate-all-around (GAA) junction-less vertical nanowire field effect transistors (VNWFET) are a promising alternative. This work analyses the energy-delay-product (EDP) for a junction-less 3D ve
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::530690b543af171c1e37f6997bc1e7a5
https://hal.archives-ouvertes.fr/hal-03407210/file/EUROSOI21_EDP_VF.pdf
https://hal.archives-ouvertes.fr/hal-03407210/file/EUROSOI21_EDP_VF.pdf
Autor:
Kenichi Kanazawa, Tetsuo Izawa, Oskar Baumgartner, Georg Strof, Yisuo Li, Koji Sakui, Zlatan Stanojevic, Nozomu Harada, Markus Karner, Gerhard Rzepa, Fujio Masuoka
Publikováno v:
2021 IEEE International Memory Workshop (IMW).
We propose the architecture and manufacturing process of 6 surrounding-gate-transistor (SGT) SRAM cell for the 1.5nm technology node. The staggered layout and self-aligned patternings have successfully realized a transition from 5nm to 1.5nm node wit