Zobrazeno 1 - 10
of 118
pro vyhledávání: '"Oscar Palomar"'
Autor:
Francesco Minervini, Oscar Palomar, Osman Unsal, Enrico Reggiani, Josue Quiroga, Joan Marimon, Carlos Rojas, Roger Figueras, Abraham Ruiz, Alberto Gonzalez, Jonnatan Mendoza, Ivan Vargas, César Hernandez, Joan Cabre, Lina Khoirunisya, Mustapha Bouhali, Julian Pavon, Francesc Moll, Mauro Olivieri, Mario Kovac, Mate Kovac, Leon Dragic, Mateo Valero, Adrian Cristal
Publikováno v:
ACM Transactions on Architecture and Code Optimization. 20:1-25
The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of specialized hardware in processor cores for the High Performance C
Autor:
Victor Jimenez, Mario Rodriguez, Marc Dominguez, Josep Sans, Ivan Diaz, Luca Valente, Vito Luca Guglielmi, Josue V. Quiroga, R. Ignacio Genovese, Nehir Sonmez, Oscar Palomar, Miquel Moreto
We present the functional verification efforts for an academic RISC-V based vector accelerator, successfully taped-out in the context of the European Processor Initiative. For our novel RISC-V based decoupled vector accelerator, we built a verificati
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f074e0a6aa009c9a6eb87a1dd3fc3ca9
https://hdl.handle.net/2117/382717
https://hdl.handle.net/2117/382717
Autor:
Guillem Cabo, Gerard Candon, Xavier Carril, Max Doblas, Marc Dominguez, Alberto Gonzalez, Cesar Hernandez, Victor Jimenez, Vatistas Kostalampros, Ruben Langarita, Neiel Leyva, Guillem Lopez-Paradis, Jonnatan Mendoza, Francesco Minervini, Julian Pavon, Cristobal Ramirez, Narcis Rodas, Enrico Reggiani, Mario Rodriguez, Carlos Rojas, Abraham Ruiz, Victor Soria, Alejandro Suanes, Ivan Vargas, Roger Figueras, Pau Fontova, Joan Marimon, Victor Montabes, Adrian Cristal, Carles Hernandez, Ricardo Martinez, Miquel Moreto, Francesc Moll, Oscar Palomar, Marco A. Ramirez, Antonio Rubio, Jordi Sacristan, Francesc Serra-Graells, Nehir Sonmez, Lluis Teres, Osman Unsal, Mateo Valero, Luis Villa
Publikováno v:
2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS).
This paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The DVINO proc
Autor:
Mate Kovač, Leon Dragić, Branimir Malnar, Francesco Minervini, Oscar Palomar, Carlos Rojas, Mauro Olivieri, Josip Knezović, Mario Kovač
We present Faust, a pipelined FPU for vector processing-capable RISC-V core developed within the EPI project. Faust is based on the open-source multi-format floating-point architecture FPnew. Our design extends the support for the RISC-V Vector exten
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::073b44ca752f7148c205b3d6064747e8
https://doi.org/10.1016/j.micpro.2023.104762
https://doi.org/10.1016/j.micpro.2023.104762
Autor:
Osman Unsal, Oscar Palomar, Cristóbal Ramírez, César Alejandro Hernández, Adrian Cristal, Marco A. Leyva Ramírez
Publikováno v:
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Universitat Politècnica de Catalunya (UPC)
Vector architectures lack tools for research. Consider the gem5 simulator, which is possibly the leading platform for computer-system architecture research. Unfortunately, gem5 does not have an available distribution that includes a flexible and cust
Publikováno v:
Journal of Parallel and Distributed Computing. 95:92-106
Thanks to programming approaches like actor-based models, message passing is regaining popularity outside large-scale scientific computing for building scalable distributed applications in multi-core processors. Unfortunately, the mismatch between me
Autor:
Oscar Palomar, Oriol Arcas-Abella, Timothy Hayes, Adria Armejach, Behzad Salami, Gorker Alp Malazgirt, Nehir Sonmez
Publikováno v:
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Universitat Politècnica de Catalunya (UPC)
Database management systems have become an indispensable tool for industry, government, and academia, and form a significant component of modern datacenters. They can be used in a multitude of scenarios, including online analytical processing, data m
Publikováno v:
Recercat. Dipósit de la Recerca de Catalunya
instname
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
instname
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
The need for power efficiency is driving a rethink of design decisions in processor architectures. While vector processors succeeded in the high-performance market in the past, they need a retailoring for the mobile market that they are entering now.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::cf82dfcec4b01a5c5a869babc8a18811
https://hdl.handle.net/2117/116231
https://hdl.handle.net/2117/116231
Publikováno v:
Digital.CSIC. Repositorio Institucional del CSIC
instname
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
instname
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
To manage power and memory wall affects, the HPC industry supports FPGA reconfigurable accelerators and vector processing cores for data-intensive scientific applications. FPGA based vector accelerators are used to increase the performance of high-pe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6e3380a743eaa1e7b2bfbd1206dc7fa4
http://hdl.handle.net/10261/197374
http://hdl.handle.net/10261/197374
Publikováno v:
Mawer, J, Palomar, O, Gorgovan, C, Nisbet, A & Luján, M 2017, The Potential of Dynamic Binary Modification and CPU-FPGA SoCs for Simulation . in The 25th IEEE International Symposium on Field-Programmable Custom Computing Machines . https://doi.org/10.1109/FCCM.2017.36
FCCM
FCCM
In this paper we describe a flexible infrastructure that can directly interface unmodified application executables with FPGA hardware acceleration IP in order to 1), facilitate faster computer architecture simulation, and 2), to prototype microarchit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f95ffc1b1da377f0cc4442661af1575e
https://pure.manchester.ac.uk/ws/files/55660049/main_19.pdf
https://pure.manchester.ac.uk/ws/files/55660049/main_19.pdf