Zobrazeno 1 - 10
of 137
pro vyhledávání: '"Orasson, A."'
Publikováno v:
In Microprocessors and Microsystems 2008 32(5):254-262
Publikováno v:
Acta Neurologica Scandinavica. Sep2001, Vol. 104 Issue 3, p148-155. 8p.
Publikováno v:
In Brain and Cognition April 1999 39(3):187-201
Publikováno v:
2016 11th European Workshop on Microelectronics Education (EWME)
EWME
EWME
We propose a tool set for teaching and e-learning the main principles of design-for-testability technics for digital systems. It is a collection of software tools which simulate a circuit under test, emulate a pool of different strategies, methods an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a9e0b8e9796a8541aac201022174e0b3
Fault Collapsing in Digital Circuits Using Fast Fault Dominance and Equivalence Analysis with SSBDDs
Publikováno v:
VLSI-SoC: Design for Reliability, Security, and Low Power
IFIP Advances in Information and Communication Technology
IFIP Advances in Information and Communication Technology-VLSI-SoC: Design for Reliability, Security, and Low Power
VLSI-SoC: Design for Reliability, Security, and Low Power ISBN: 9783319460963
VLSI-SoC (Selected Papers)
IFIP Advances in Information and Communication Technology
IFIP Advances in Information and Communication Technology-VLSI-SoC: Design for Reliability, Security, and Low Power
VLSI-SoC: Design for Reliability, Security, and Low Power ISBN: 9783319460963
VLSI-SoC (Selected Papers)
The paper presents a new method and an algorithm for structural fault collapsing to reduce the search space for test generation, to speed up fault simulation and to make the fault diagnosis easier in digital circuits. The proposed method is based on
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f167905350a794ffd130416e55cef82f
Publikováno v:
2016 11th European Workshop on Microelectronics Education (EWME); 2016, p1-6, 6p
Publikováno v:
VLSI-SoC: Design for Reliability, Security & Low Power; 2016, p23-45, 23p
Autor:
Kruus, H., Ubar, R., Ellervee, P., Gorev, M., Pesonen, V., Devadze, S., Orasson, E., Brik, M., Min, M., Annus, P., Kruus, M., Meigas, K.
Publikováno v:
2012 13th Biennial Baltic Electronics Conference; 1/ 1/2012, p85-88, 4p
Autor:
Kuzmicz, Wieslaw1 (AUTHOR) wieslaw.kuzmicz@pw.edu.pl
Publikováno v:
International Journal of Electrical Engineering Education. Oct2024, Vol. 61 Issue 4, p452-462. 11p.
Publikováno v:
Microprocessors and Microsystems. 32:254-262
Classical built-in self-test (BIST) approaches are largely based on pseudorandom testing, and using linear feedback shift registers (LFSR) for test set generation and test response compaction. In this paper, we are concentrating on one possible exten
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7b6d78165ec7f0f6f0c417ded762979d
https://doi.org/10.1016/j.micpro.2008.03.007
https://doi.org/10.1016/j.micpro.2008.03.007