Zobrazeno 1 - 10
of 34
pro vyhledávání: '"Operand forwarding"'
Autor:
Jonathan Bailey, Trevor Mudge, Scott Mahlke, Jonathan Beaumont, John Kloosterman, D. Anoushe Jamshidi
Publikováno v:
MICRO
The register file is one of the largest and most power-hungry structures in a Graphics Processing Unit (GPU), because massive multithreading requires all the register state for every active thread to be available. Previous approaches to making regist
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::77bf66081f346a3a2c4c72e3b70f6098
https://doi.org/10.1145/3123939.3123974
https://doi.org/10.1145/3123939.3123974
Publikováno v:
AINA Workshops
This paper describes the verification plan on data hazard detection and handling for a 32-bit MIPS ISA (Microprocessor without Interlocked Pipeline Stages Instruction Set Architecture) compatible 5-stage pipeline processor, RISC32. Our work can be us
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c30f91dbffa0cf5c88aceae5f285a9fa
https://strathprints.strath.ac.uk/61831/1/Kiat_etal_IEEE_WAINA_2017_A_comprehensive_analysis_on_data_hazard_for_RISC32_5_Stage.pdf
https://strathprints.strath.ac.uk/61831/1/Kiat_etal_IEEE_WAINA_2017_A_comprehensive_analysis_on_data_hazard_for_RISC32_5_Stage.pdf
Autor:
Hoi-Jun Yoo, Byeong-Gyu Nam
Publikováno v:
IEEE Journal of Solid-State Circuits. 44:1554-1570
A low-power and high-performance 4-way 32-bit stream processor core is developed for handheld low-power 3-D graphics systems. It contains a floating-point unified matrix, vector, and elementary function unit. By exploiting the logarithmic arithmetic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::62327d0feb4dc338bf6a6b7449b7e7a5
https://doi.org/10.1109/jssc.2009.2016698
https://doi.org/10.1109/jssc.2009.2016698
Publikováno v:
IEEE Computer Architecture Letters. 8:60-63
Operand register files are small, inexpensive register files that are integrated with function units in the execute stage of the pipeline, effectively extending the pipeline operand registers into register files. Explicit operand forwarding lets soft
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6332ea97c1776df9d49c2747587019d8
https://doi.org/10.1109/l-ca.2009.45
https://doi.org/10.1109/l-ca.2009.45
Publikováno v:
Journal of Electronics (China). 24:157-162
Recent advances in broadband technology have caused forwarding engines to handle packets with over 10 gigabit per second. In this paper, we present a high-speed forwarding pipeline which can finish all of the routing and forwarding tasks in the way o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6e6d48eaa5314c9ca14a05fe69edc63e
https://doi.org/10.1007/s11767-005-0148-0
https://doi.org/10.1007/s11767-005-0148-0
Publikováno v:
2015 18th CSI International Symposium on Computer Architecture and Digital Systems (CADS).
Transport triggered architecture processors may have function unit input registers, which allow operands to be written to function units earlier than the clock cycle where the operation begins execution. An operand used in consecutive operations may
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::35c58969cde1920472801235851b754b
https://doi.org/10.1109/cads.2015.7377786
https://doi.org/10.1109/cads.2015.7377786
Autor:
Paolo Bernardi, M. Sonza Reorda, Michelangelo Grosso, O. Ballan, L. Ciganda, Eladio F. Sanchez, Riccardo Cantoro, Boyang Du
Publikováno v:
MTV
When the result of a previous instruction is needed in the pipeline before it is available, a "data hazard" occurs. Register Forwarding and Pipeline Interlock (RFaPI) are mechanisms suitable to avoid data corruption and to limit the performance penal
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::22030bfd3ad63394a101b1c70d402b70
http://hdl.handle.net/11583/2525509
http://hdl.handle.net/11583/2525509
Publikováno v:
Journal of Systems Architecture. 46:749-764
Register bypassing, universally provided in synchronous processors, is more difficult to implement in an asynchronous design. Asynchronous bypassing requires synchronization between the forwarding and receiving units, with the danger that the advanta
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e4de837e52c78cb8c4007f1f55f19303
https://doi.org/10.1016/s1383-7621(99)00029-6
https://doi.org/10.1016/s1383-7621(99)00029-6
Publikováno v:
IEEE Transactions on Computers. 49:33-47
This paper presents a floating-point addition algorithm and adder pipeline design employing a packet forwarding pipeline paradigm. The packet forwarding format and the proposed algorithms constitute a new paradigm for handling data hazards in deeply
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2fef91f4c2ec585b15067dd290795420
https://doi.org/10.1109/12.822562
https://doi.org/10.1109/12.822562
Autor:
L. Ciganda, D. Boyang, O. Ballan, Michelangelo Grosso, Eladio F. Sanchez, Paolo Bernardi, M. Sonza Reorda
Publikováno v:
IDT
When the result of a previous instruction is needed in the pipeline before it is available, a “data hazard” occurs. Register Forwarding and Pipeline Interlock (RFP its test can hardly be achieved with a functional approach, unless a specific test
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::350c4374b3338f95d9423fecac4a27e4
http://hdl.handle.net/11583/2505588
http://hdl.handle.net/11583/2505588